--- title: "Timing diagram of STA 8050H" subject: "Microprocessor" chapter: 2 key: "semester_4/microprocessor:timing-sta-8050h" source: https://www.bctengineer.com/q/semester_4/microprocessor/timing-sta-8050h site: BCT Engineering --- # Timing diagram of STA 8050H Microprocessor · Chapter 2: Programming with 8085 Microprocessor - Asked in: 2073 Bhadra, 2+6 marks - Video: [Timing diagram of STA instruction | STA instruction timing diagram | STA instruction in 8085](https://www.youtube.com/watch?v=pgU7IvE5PsE) — Scratch Learners - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/timing-sta-8050h - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2 ## Question Explain bus timing diagram. Draw and explain the timing diagram of the 8085 instruction STA 8050H. ## Short answer A bus timing diagram depicts address, data, and control signals per T-state. STA 8050H uses four cycles: opcode fetch, two memory reads to get 50H and 80H forming address, and a memory write to store A at 8050H; total 13 T-states. ## Answer #### Bus timing diagram A **bus timing diagram** shows the state of the address lines, data lines and control signals (ALE, RD, WR, IO/M, S1, S0) against the clock, T-state by T-state, during one machine cycle. It tells exactly when the address is valid, when data is read or written and which device is selected. It is used to design memory/I/O interfaces and to check timing requirements. Basic pattern of an opcode fetch cycle (4T): ```text | T1 | T2 | T3 | T4 | CLK | _|-|_| _|-|_| _|-|_| _|-|_ | ALE | HIGH| low | low | low | A15-A8 | PCH (address valid ........| AD7-0 | PCL | -- |opcode| -- | RD | high| LOW | LOW | high | IO/M | low (memory operation) | ``` #### STA 8050H `STA 8050H` (opcode 32H) stores the accumulator into memory location 8050H. It is a 3-byte instruction with 4 machine cycles: opcode fetch (4T), memory read (3T), memory read (3T), memory write (3T), total **13 T-states**. Assume it is stored at 2000H: bytes 32H, 50H, 80H. | M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 | |---|---|---|---|---|---|---| | **M1 (opcode fetch, 4T)** | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 | | | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 | | | T3 | 20H | 32H (opcode in) | 0 | RD low, rises at end | 0 1 1 | | | T4 | - | - | 0 | none (decode) | 0 1 1 | | **M2 (memory read, 3T)** | T1 | 20H | 01H | 1 | - | 0 1 0 | | | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | | | T3 | 20H | 50H (data in) | 0 | RD low, rises at end | 0 1 0 | | **M3 (memory read, 3T)** | T1 | 20H | 02H | 1 | - | 0 1 0 | | | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | | | T3 | 20H | 80H (data in) | 0 | RD low, rises at end | 0 1 0 | | **M4 (memory write, 3T)** | T1 | 80H | 50H | 1 | - | 0 0 1 | | | T2 | 80H | A (data out) | 0 | WR low | 0 0 1 | | | T3 | 80H | A | 0 | WR low, rises at end | 0 0 1 | #### Explanation - **M1 (opcode fetch)**: PC = 2000H on the bus, ALE high in T1; RD low in T2-T3; opcode 32H is read into IR and decoded in T4. - **M2 (memory read)**: address 2001H; RD low; low-order address byte 50H goes to register Z. - **M3 (memory read)**: address 2002H; RD low; high-order address byte 80H goes to register W. - **M4 (memory write)**: WZ = 8050H is put on the bus (80H on A15-A8, 50H on AD7-AD0 with ALE high in T1). In T2 the CPU places the content of A on AD7-AD0 and WR goes low; the memory stores the data when WR rises at the end of T3. IO/M = 0, S1 = 0, S0 = 1. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does a bus timing diagram show? A. The state of address lines, data lines and control signals against the clock, T-state by T-state B. The order in which instructions are stored in memory C. The flowchart of the program being executed D. The internal block diagram of the CPU Answer: A. A timing diagram shows each bus and control signal (ALE, RD, WR, IO/M, S1, S0) against the clock, so you can see when the address is valid and when data moves. (Key point: Timing diagram shows bus and control signals against the clock, T-state by T-state) 2. What are the machine cycles of STA 8050H and the total T-states? A. Opcode fetch + memory read + memory read = 10 T-states B. Opcode fetch + memory write = 7 T-states C. Opcode fetch + memory read + memory read + memory write = 13 T-states D. Opcode fetch + memory read + memory write + memory write = 13 T-states Answer: C. After the opcode fetch (4T), two memory reads (3T each) bring in the address bytes 50H and 80H, and one memory write (3T) stores A. Total 4 + 3 + 3 + 3 = 13. (Key point: STA 8050H = OF + MR + MR + MW = 13 T-states) 3. In the memory write cycle (M4) of STA 8050H stored at 2000H, which address is put on the bus? A. 2003H, the next value of PC B. 8050H, from the W and Z registers C. 5080H, because the bytes were read low first D. 2002H, the last byte of the instruction Answer: B. M2 reads 50H into Z and M3 reads 80H into W. In M4, WZ = 8050H is placed on the bus (80H on A15-A8, 50H on AD7-AD0). (Key point: In M4 the address 8050H comes from WZ, not PC) 4. During M4 of STA 8050H, what are IO/M, S1, S0 and which control line goes low? A. IO/M = 0, S1 = 1, S0 = 0; RD goes low B. IO/M = 1, S1 = 0, S0 = 1; WR goes low C. IO/M = 0, S1 = 1, S0 = 1; RD goes low D. IO/M = 0, S1 = 0, S0 = 1; WR goes low Answer: D. It is a memory (IO/M = 0) write (S1 S0 = 01). The CPU puts A on AD7-AD0 and WR goes low, and the memory stores the data when WR rises at the end of T3. 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