--- title: "Timing diagram of STA, program time" subject: "Microprocessor" chapter: 2 key: "semester_4/microprocessor:timing-sta-program-time" source: https://www.bctengineer.com/q/semester_4/microprocessor/timing-sta-program-time site: BCT Engineering --- # Timing diagram of STA, program time Microprocessor · Chapter 2: Programming with 8085 Microprocessor - Asked in: 2072 Magh, 5+3 marks - Video: [Timing Diagram of STA Instruction in 8085 Microprocessor | Timing Diagram](https://www.youtube.com/watch?v=41bhvsdyyXI) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/timing-sta-program-time - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2 ## Question Draw the timing diagram of STA instruction. Calculate the time taken to execute the following program if T = 1 micro second. MVI A,05H ADI 20H OUT 80H HLT ## Short answer The program consists of MVI A,05H (7T), ADI 20H (7T), OUT 80H (10T), and HLT (5T), totaling 29 T-states. With T=1 µs, execution time is 29 µs. ## Answer #### Timing diagram of STA `STA addr` (opcode 32H) stores A at the 16-bit address given in the instruction. It has four machine cycles: opcode fetch (4T), memory read for the low address byte (3T), memory read for the high address byte (3T), memory write (3T) = 13T. Assume `STA 8050H` stored from 2000H. | M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 | |---|---|---|---|---|---|---| | **M1 (opcode fetch, 4T)** | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 | | | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 | | | T3 | 20H | 32H (opcode in) | 0 | RD low, rises at end | 0 1 1 | | | T4 | - | - | 0 | none (decode) | 0 1 1 | | **M2 (memory read, 3T)** | T1 | 20H | 01H | 1 | - | 0 1 0 | | | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | | | T3 | 20H | 50H (data in) | 0 | RD low, rises at end | 0 1 0 | | **M3 (memory read, 3T)** | T1 | 20H | 02H | 1 | - | 0 1 0 | | | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | | | T3 | 20H | 80H (data in) | 0 | RD low, rises at end | 0 1 0 | | **M4 (memory write, 3T)** | T1 | 80H | 50H | 1 | - | 0 0 1 | | | T2 | 80H | A (data out) | 0 | WR low | 0 0 1 | | | T3 | 80H | A | 0 | WR low, rises at end | 0 0 1 | ```text | M1 (OF) | M2 (MR) | M3 (MR) | M4 (MW) | |T1 T2 T3 T4|T1 T2 T3 |T1 T2 T3 |T1 T2 T3 | ALE |HI lo lo lo|HI lo lo |HI lo lo |HI lo lo | RD |hi LO LO hi|hi LO LO |hi LO LO |hi hi hi | WR |hi hi hi hi|hi hi hi |hi hi hi |hi LO LO | ``` #### Execution time of the program T = 1 microsecond. | Instruction | Machine cycles | T-states | |---|---|---| | MVI A,05H | OF (4) + MR (3) | 7 | | ADI 20H | OF (4) + MR (3) | 7 | | OUT 80H | OF (4) + MR (3) + IOW (3) | 10 | | HLT | OF (5) | 5 | | **Total** | | **29** | Time = 29 x 1 microsecond = **29 microseconds**. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which machine cycles make up the STA addr instruction? A. Opcode fetch, memory read, memory write (10T) B. Opcode fetch, memory write, memory write (10T) C. Opcode fetch (4T), memory read (3T), memory read (3T), memory write (3T) = 13T D. Opcode fetch (4T), memory read (3T), memory read (3T), memory read (3T) = 13T Answer: C. STA fetches its opcode, reads the low and high bytes of the address, and then writes A to that address in a memory write cycle. That gives 4 + 3 + 3 + 3 = 13T. (Key point: STA = opcode fetch + 2 memory reads + memory write = 13T) 2. For STA 8050H stored at 2000H, what is on the address bus in M4, and which control signal is active? A. 2003H, with RD low B. 8050H, with WR low C. 8050H, with RD low D. 2003H, with WR low Answer: B. M4 is a memory write to the operand address 8050H (A15-A8 = 80H, AD7-AD0 = 50H in T1). WR goes low while A is output on the data bus, and IO/M S1 S0 = 0 0 1. (Key point: In the STA write cycle, the operand address is on the bus and WR is low) 3. How many T-states does OUT 80H take? A. 7: opcode fetch (4) + memory read (3) B. 4: opcode fetch only C. 13: opcode fetch (4) + three 3T cycles D. 10: opcode fetch (4) + memory read (3) + I/O write (3) Answer: D. OUT 80H fetches its opcode (4T), reads the port address 80H (3T), and then sends A to the port in an I/O write cycle (3T), for a total of 10T. (Key point: OUT port = OF + MR + IOW = 10 T-states) 4. With T = 1 microsecond, how long does MVI A,05H / ADI 20H / OUT 80H / HLT take? A. 29 microseconds B. 28 microseconds C. 26 microseconds D. 24 microseconds Answer: A. MVI takes 7T, ADI 7T, OUT 10T and HLT 5T, for a total of 29T. At 1 microsecond per T-state, that is 29 microseconds. Taking HLT as 4T would wrongly give 28. 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