--- title: "Unique/non-unique decoding, memory mapped I/O" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:unique-nonunique-decoding-memory-mapped-io" source: https://www.bctengineer.com/q/semester_4/microprocessor/unique-nonunique-decoding-memory-mapped-io site: BCT Engineering --- # Unique/non-unique decoding, memory mapped I/O Microprocessor · Chapter 4: Microprocessor System - Asked in: 2068 Bhadra, 2+6 marks - Video: [Address Decoding](https://www.youtube.com/watch?v=nOMyv79cqKQ) — AAkrit Subedi - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/unique-nonunique-decoding-memory-mapped-io - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question What do you mean by unique and non-unique address decoding? Explain memory mapped I/O along with an example. ## Short answer Unique decoding uses all address lines so each location has one address; non-unique decoding ignores some lines, causing mirror addresses and wasted space. Memory mapped I/O gives a device a memory address and uses memory instructions; for example, an output port at 8000H is written with STA 8000H. ## Answer #### Unique and non-unique decoding **Address decoding** is the process of generating a chip-select signal from the address lines so that a memory or I/O device responds only to its own addresses. - **Unique (absolute, full) decoding:** all address lines (A0–A15 for a 16-bit address) are used, either to select the chip or inside the chip. Each device location responds to exactly one address. It needs more decoding hardware but wastes no address space. - **Non-unique (partial) decoding:** some higher-order address lines are ignored (don't care). The same device responds to more than one address (a "foldback" or mirror image). The hardware is simpler and cheaper, but part of the address space is wasted, and the mirrored addresses cannot be given to any other device. Example: an I/O port decoded with only A15 and A14 responds to every address whose A15A14 = 10, i.e. 8000H–BFFFH, so the decoding is non-unique. #### Memory mapped I/O In memory mapped I/O the I/O device is given a memory address and is accessed with memory instructions and the memory control signals MEMR/MEMW (IO/M = 0). All 16 address lines are decoded. **Example:** an 8-bit output port (8-bit latch such as the 74LS373) at address **8000H** on the 8085, with unique decoding: ```text A14..A0 -> [15-input NOR] -> X (1 when all are 0) A15 ---------------------\ X -----------------------> [AND] -> SEL (address = 8000H) IO/M' = 0 (memory cycle) and WR' = 0 -> MEMW active LE (latch enable, active high) = AND(SEL, MEMW active) OE' of the latch tied to ground (outputs always enabled) D0-D7 -> [74LS373 latch] -> output port ``` Condition: A15 = 1, A14–A0 = 0, IO/M = 0, WR = 0 → latch enabled; the data on D0–D7 is latched to the port. **Program:** ```asm MVI A,55H ; data to output STA 8000H ; write to the port (memory write cycle) LDA 8000H ; read back only if an input port is also decoded at 8000H ``` Because the port is in the memory map, the address 8000H cannot be used by memory, and any memory-reference instruction (e.g. `MOV M,A` with HL = 8000H) can also access it. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is non-unique (partial) decoding? A. All address lines are decoded B. Some higher-order lines are ignored, so the device responds to more than one address C. The device never responds D. The chip select is made from data lines Answer: B. With partial decoding the don't-care lines make the device appear at several (mirrored) addresses, saving hardware but wasting address space. (Key point: Non-unique decoding) 2. An I/O port decoded using only A15 and A14 with A15A14 = 10 responds to which range? A. 8000H only B. 0000H-3FFFH C. 8000H-BFFFH D. C000H-FFFFH Answer: C. A15A14 = 10 covers all addresses from 8000H to BFFFH, so the decoding is non-unique. (Key point: Example range) 3. How is a memory mapped I/O port accessed? A. Like memory, with memory instructions and MEMR/MEMW (IO/M = 0) B. Only with IN and OUT C. Only through the accumulator with IO/M = 1 D. By DMA only Answer: A. The port has a memory address, so instructions such as STA, LDA and MOV M,A work and the memory control signals are used. (Key point: Memory mapped access) 4. For a unique-decoded output port at 8000H, which condition enables the latch? A. A15 = 0, A14-A0 = 1, IO/M = 1 B. A15 = 1, A14-A0 = 1, RD = 0 C. Only A15 = 1 D. A15 = 1, A14-A0 = 0, IO/M = 0 and WR = 0 Answer: D. 8000H has A15 = 1 and all other lines 0; it is a memory write so IO/M = 0 and WR = 0. (Key point: Port at 8000H) ## Related in Microprocessor - [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4 - [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4 - [Short note: I/O mapped and memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aio-mapped-memory-mapped-io) — Microprocessor, chapter 4 - [Address decoding for 8 LEDs output port](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-output-port-8-leds) — Microprocessor, chapter 4 - [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4 - [Address decoding for input port at 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-port-lda-8050h) — Microprocessor, chapter 4 ## Related in other subjects - [Unique vs non-unique address decoding](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aunique-vs-nonunique-decoding) — Instrumentation II, chapter 2 - [Full vs partial address decoding for memory](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Afull-vs-partial-decoding) — Instrumentation II, chapter 2 - [Memory-mapped I/O reduces address space](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ammio-address-space) — Computer Organization and Architecture, chapter 7 - [Memory-mapped I/O design for 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Amemmapped-io-design-1000h) — Instrumentation II, chapter 2