--- title: "Effect of bundled conductors on L and C" subject: "Power System Analysis I" chapter: 4 key: "semester_4/power_system_analysis_i:bundled-conductor-effect-l-c" source: https://www.bctengineer.com/q/semester_4/power_system_analysis_i/bundled-conductor-effect-l-c site: BCT Engineering --- # Effect of bundled conductors on L and C Power System Analysis I · Chapter 4: Line Parameter Calculations - Asked in: 2076 Baisakh, 6 marks - Video: [33. Bundled Conductors](https://www.youtube.com/watch?v=RkRWQdTsm6U) — Bright Engineers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/power_system_analysis_i/bundled-conductor-effect-l-c - Whole chapter: https://www.bctengineer.com/md/semester_4/power_system_analysis_i/chapter-4 ## Question What are bundled conductors? How does the use of bundled conductors affect capacitance and inductance compared to a line with a single conductor? ## Short answer Bundled conductors are two or more sub-conductors per phase. They increase the effective radius, reducing inductance and increasing capacitance per phase. This lowers series reactance, raises charging current, and increases surge impedance loading. ## Answer A **bundled conductor** is a phase conductor made of two or more sub-conductors (usually 2, 3 or 4) in parallel, held a short distance apart (about 30–50 cm) by spacers. Bundling is used on EHV lines (220 kV and above). ```text 2-bundle 3-bundle 4-bundle o---o o o---o d / \ | | o---o o---o ``` #### Self GMD of a bundle | Bundle | $D_s$ for $L$ | $D_s$ for $C$ | |---|---|---| | 2 | $\sqrt{r'd}$ | $\sqrt{rd}$ | | 3 | $\sqrt[3]{r'd^2}$ | $\sqrt[3]{rd^2}$ | | 4 | $1.09\sqrt[4]{r'd^3}$ | $1.09\sqrt[4]{rd^3}$ | Since $d \gg r$, the bundle's self-GMD is many times larger than the radius of a single conductor. #### Effect on inductance $$ L = 2\times10^{-7}\ln\frac{D_m}{D_s} $$ A larger $D_s$ makes $\ln(D_m/D_s)$ smaller, so **inductance per phase decreases** (typically by 25–35% for a 2–4 bundle). Lower series reactance raises the power transfer limit ($P_{max} = V_SV_R/X$) and improves voltage regulation and stability. #### Effect on capacitance $$ C = \frac{2\pi\varepsilon_0}{\ln(D_m/D_s)} $$ The same larger $D_s$ makes the denominator smaller, so **capacitance per phase increases**. Charging current rises, but surge impedance $Z_c = \sqrt{L/C}$ falls, so the **surge impedance loading** ($V^2/Z_c$) increases. #### Example For $r = 2$ cm, $D_m = 12.6$ m, a single conductor gives $L = 2\times10^{-7}\ln(12.6/0.0156) = 1.34$ mH/km; a twin bundle with $d = 40$ cm gives $D_s = \sqrt{0.0156\times0.4} = 0.079$ m and $L = 1.01$ mH/km. #### Other benefits - Lower surface voltage gradient, so less corona loss and radio interference. - Higher current capacity per phase and lower reactance. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is a bundled conductor? A. Several phases laid in one cable B. A phase conductor made of two or more sub-conductors held a short distance apart by spacers C. A conductor with a steel core D. Two circuits on the same tower Answer: B. Sub-conductors (2, 3 or 4) in parallel spaced about 30-50 cm by spacers form one phase, used on EHV lines. (Key point: Bundle definition) 2. Why does bundling reduce inductance per phase? A. It reduces current B. It increases D_s, so ln(D_m/D_s) is smaller C. It reduces D_m D. It increases the permeability Answer: B. D_s is many times the single radius, so the log term and L = 2e-7 ln(D_m/D_s) decrease. (Key point: Effect on inductance) 3. How does bundling affect capacitance per phase? A. It decreases it B. No change C. It increases it D. It becomes zero Answer: C. A larger D_s makes the denominator of C = 2*pi*eps0/ln(D_m/D_s) smaller, so C increases. (Key point: Effect on capacitance) 4. What happens to surge impedance and surge impedance loading with bundling? A. Z_c rises and SIL falls B. Z_c falls and SIL rises C. Both rise D. Both unchanged Answer: B. L falls and C rises so Z_c = sqrt(L/C) falls, and SIL = V^2/Z_c increases. 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