--- title: "Practical sampling; band-pass sampling" subject: "Signals and Systems" chapter: 4 key: "semester_4/signals_and_systems:practical-bandpass-sampling" source: https://www.bctengineer.com/q/semester_4/signals_and_systems/practical-bandpass-sampling site: BCT Engineering --- # Practical sampling; band-pass sampling Signals and Systems · Chapter 4: Sampling - Asked in: 2078 Poush, 4+2 marks - Video: [Sampling Types in digital communication - Ideal, Natural, Flat top Sampling - Aperture effect](https://www.youtube.com/watch?v=sFiCgEVpTWs) — Electronics Subjectified - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/signals_and_systems/practical-bandpass-sampling - Whole chapter: https://www.bctengineer.com/md/semester_4/signals_and_systems/chapter-4 ## Question Explain practical sampling method using a circuit diagram. Describe band-pass sampling theorem. ## Short answer Practical sampling uses a sample-and-hold circuit where a FET switch charges a capacitor to the input value, held by a buffer, producing flat-top samples. The band-pass sampling theorem states a band-pass signal of bandwidth B can be sampled at a rate as low as 2B if f_s satisfies 2f_H/k ≤ f_s ≤ 2f_L/(k-1) for integer k ≤ f_H/B. ## Answer #### Practical sampling Ideal impulses cannot be generated, so in practice sampling is done with **pulses of finite width** using an electronic switch (natural sampling) or a **sample-and-hold (S/H) circuit** (flat-top sampling). **Sample-and-hold circuit:** ```text S (FET switch) buffer x(t) ---[ buffer ]---o/ o----+----[ > ]----> xs(t) ^ | sampling pulse | === C (hold (period T) | capacitor) GND ``` **Working:** 1. **Sample mode:** a short sampling pulse closes the switch S (a FET). The capacitor $C$ charges quickly to the input value $x(nT)$ through the low output resistance of the input buffer. 2. **Hold mode:** the switch opens. The capacitor holds the voltage for the rest of the period $T$ because the output buffer has very high input impedance. The output is a staircase (flat-top samples), which the ADC then converts. 3. Mathematically, flat-top sampling = ideal sampling followed by a hold filter $h(t)$ (a pulse of width $\tau$). Its spectrum is $X_s(j\omega) = \frac{1}{T}H(j\omega)\sum_k X(j(\omega - k\omega_s))$, with $H(j\omega) = \tau\,\text{sinc}$-shaped. This causes the **aperture effect** (slight high-frequency loss), corrected with an equalizer $1/H(j\omega)$ at reconstruction. With **natural sampling** (switch only, no capacitor), the pulse tops follow the signal and the spectrum copies are only weighted by constants, so no aperture distortion occurs. #### Band-pass sampling theorem For a band-pass signal occupying $f_L$ to $f_H$ with bandwidth $B = f_H - f_L$, sampling at $2f_H$ is not necessary. The signal can be recovered from samples taken at a rate as low as $2B$, provided $$ \frac{2f_H}{k} \le f_s \le \frac{2f_L}{k-1}, \qquad k = 1, 2, \dots, \left\lfloor\frac{f_H}{B}\right\rfloor $$ In particular, if $f_H$ is an integer multiple of $B$, then $f_s = 2B$ works. **Example:** a signal from 20 to 25 kHz ($B = 5$ kHz, $f_H = 5B$) can be sampled at 10 kHz instead of 50 kHz. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why is ideal impulse sampling replaced in practice? A. Impulses give too little bandwidth B. Impulses cause too much delay C. Ideal impulses cannot be generated; finite-width pulses or sample-and-hold is used D. Impulses cannot be sampled Answer: C. Practical sampling uses a switch or S/H circuit. (Key point: Why practical) 2. In the S/H circuit's hold mode A. The switch closes and the capacitor charges B. The capacitor discharges to ground C. The output buffer disconnects D. The switch opens and the capacitor holds the voltage Answer: D. High input impedance of the output buffer keeps the voltage constant. (Key point: Hold mode) 3. Flat-top sampling causes A. A slight high-frequency loss (aperture effect) fixed by an equalizer 1/H(jω) B. Aliasing at all frequencies C. A DC offset D. Time delay only Answer: A. The hold pulse has a sinc-shaped H(jω). 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