--- title: "Address sequencing for control memory" subject: "Computer Organization and Architecture" chapter: 3 key: "semester_5/computer_organization_and_architecture:address-sequencer" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/address-sequencer site: BCT Engineering --- # Address sequencing for control memory Computer Organization and Architecture · Chapter 3: Control Unit - Asked in: 2076 Chaitra, 8 marks; 2072 Chaitra, 7 marks; 2072 Kartik, 5 marks; 2071 Chaitra, 3+7 marks; 2069 Chaitra, 10 marks; 2068 Chaitra, 7 marks; 2067 Asar (old course), 3 marks (asked 7 times) - Video: [Address Sequencing || Microprogram Sequencer || Computer Organization Architecture](https://www.youtube.com/watch?v=nxNytEYQLKI) — Sudhakar Atchala - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/address-sequencer - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-3 ## Question What is address sequencing? Explain the selection of address for control memory with a block diagram. ## Short answer Address sequencing selects the next microinstruction address in control memory. The next address can come from CAR+1, a branch address field, mapping logic (opcode to start address), or the subroutine register for returns. The multiplexer selects based on condition and branch type. ## Answer #### Address sequencing Address sequencing is the process of choosing the address of the next microinstruction in the control memory. The control memory holds the microprogram, in which microinstructions are stored in groups called routines (the fetch routine, one execute routine for each instruction, and so on). The control address register (CAR) holds the address of the microinstruction currently being read. Sequencing must handle normal sequential execution, branches, entry into a routine from the opcode, and subroutine call and return. #### Selection of the next address The next address is selected from one of four sources: 1. **Incrementing CAR** (CAR + 1): the next microinstruction in sequence. 2. **Branch address field:** an unconditional or a conditional branch loads the address (AD) field of the current microinstruction into CAR when the tested condition is true; otherwise CAR is incremented. 3. **Mapping:** the opcode bits of the instruction are converted by a mapping logic (ROM or logic circuit) to the starting address of the microprogram routine. For a 4-bit opcode and a 7-bit address: 0 xxxx 00. 4. **Subroutine register (SBR):** on CALL, the return address (CAR + 1) is saved in SBR and the branch address is loaded; on RETURN, SBR is loaded into CAR. ```text Instruction code (opcode) | +------v------+ | Mapping | | logic | +------+------+ | mapped address v Status bits +-----------------+ (I, S, Z) | |<---- Branch address (AD field) | | Multiplexer |<---- Return address (SBR) +---v----+select| (next address) |<---- CAR + 1 --------+ | Branch |----->| | | | logic | +--------+--------+ | +---^----+ v | | +-------------+ +-------------+ | | CD, BR | CAR |----->| Incrementer |---+--> SBR (on CALL) | +------+------+ +-------------+ | v | +-------------+ | | Control | | | memory | | +------+------+ | v +------- microinstruction (microoperations, CD, BR, AD) ``` #### Control of selection The CD (condition) field picks a status bit (I, S, Z or the constant 1), and the BR (branch) field gives the type of branch: JMP, CALL, RET or MAP. For JMP or CALL, if the selected condition is true the next address is AD; if it is false, it is CAR + 1. RET takes the address from SBR, and MAP takes the output of the mapping logic. At power-on, the initial address (for example 64, the start of the fetch routine) is loaded into CAR. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is address sequencing? A. Choosing the next machine instruction in main memory B. Assigning addresses to operands C. Converting opcode to binary D. Choosing the address of the next microinstruction in the control memory Answer: D. Address sequencing selects the next control memory address, held in CAR. (Key point: Address sequencing) 2. Which is NOT one of the four sources of the next control address? A. The program counter PC B. CAR + 1 C. Mapped address from the opcode D. Subroutine register SBR Answer: A. The four sources are CAR+1, branch AD field, mapping logic and SBR; PC is main-memory related. (Key point: Sources of next address) 3. What does the mapping logic do? A. Increments CAR B. Converts the opcode into the starting address of the instruction's routine (e.g. 0 xxxx 00) C. Saves the return address D. Tests the status bits Answer: B. Mapping turns the 4-bit opcode into a 7-bit routine start address. (Key point: Mapping) 4. What happens on CALL and RET? A. CALL loads SBR into CAR; RET saves CAR+1 B. Both load the mapping output C. CALL saves CAR+1 in SBR and branches; RET loads SBR into CAR D. CALL increments CAR; RET resets CAR to 64 Answer: C. The subroutine register holds the return address so shared routines can be reused. (Key point: CALL and RET) ## Related in Computer Organization and Architecture - [Address sequencing capabilities of control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-sequencing-capabilities) — Computer Organization and Architecture, chapter 3 - [Memory-mapped I/O reduces address space](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ammio-address-space) — Computer Organization and Architecture, chapter 7 - [Organization of control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acontrol-memory-org) — Computer Organization and Architecture, chapter 3 - [Control memory vs main memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acontrol-vs-main-memory) — Computer Organization and Architecture, chapter 3 - [Direct mapping with 32-block memory, 8-block cache](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example) — Computer Organization and Architecture, chapter 6, asked 3× - [Direct mapping with 32-block memory, 10 blocks used](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example-10) — Computer Organization and Architecture, chapter 6, asked 3× ## Related in other subjects - [PID control operation with block diagram](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Apid-operation-block-diagram) — Embedded System, chapter 7, asked 4× - [Closed loop control system block diagram explained](https://www.bctengineer.com/question.md?key=semester_3%2Fcontrol_systems%3Awhat-is-cs-bd-closed-loop) — Control Systems, chapter 1, asked 4× - [Digital control system block diagram and advantages](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Adcs-block-diagram-advantages) — Digital Control System, chapter 1, asked 3× - [Functional block diagram of excitation control](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_plant_equipment%3Aexcitation-control-block-diagram) — Power Plant Equipment, chapter 3