---
title: "Address sequencing capabilities of control memory"
subject: "Computer Organization and Architecture"
chapter: 3
key: "semester_5/computer_organization_and_architecture:address-sequencing-capabilities"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/address-sequencing-capabilities
site: BCT Engineering
---

# Address sequencing capabilities of control memory

Computer Organization and Architecture · Chapter 3: Control Unit

- Asked in: 2067 Asar (old course), 5 marks
- Video: [Address Sequencing || Microprogram Sequencer || Computer Organization Architecture](https://www.youtube.com/watch?v=nxNytEYQLKI) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/address-sequencing-capabilities
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-3

## Question

Explain the address sequencing capabilities required in a control memory.

## Short answer

The sequencer must increment CAR, branch unconditionally, branch conditionally on status bits, map opcode to routine start address, support subroutine call/return with SBR, and load initial fetch address. A multiplexer selects between CAR+1, the AD field, SBR, or mapping logic based on CD and BR fields.

## Answer

The control memory holds microprograms made of routines. The address sequencing hardware must be able to do the following.

1. **Incrementing the control address register:** after each microinstruction, CAR ← CAR + 1 to follow the routine in sequence.
2. **Unconditional branch:** load CAR with the branch address from the AD field (BR = JMP, CD = U).
3. **Conditional branch:** test a status bit (I, S, Z, carry); if true, CAR ← AD, else CAR ← CAR + 1. This gives decisions in the microprogram.
4. **Mapping of instruction:** the opcode of the machine instruction is converted into the starting address of its routine in the control memory (for a 4-bit opcode: 0 xxxx 00).
5. **Subroutine call and return:** CALL stores the return address (CAR + 1) in the subroutine register (SBR) and branches; RET loads CAR from SBR. Common routines (like indirect address calculation) can be shared.
6. **Initial address:** on reset, CAR loads the address of the first microinstruction (the fetch routine).

A multiplexer selects among CAR + 1, the AD field, SBR and the mapping logic under control of the CD and BR fields.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does a conditional branch do when the bit is 0?
   A. CAR<-AD
   B. CAR<-CAR+1
   C. CAR<-SBR
   D. CAR cleared
   Answer: B. Only if true loads AD. (Key point: Conditional)

2. Mapping for 4-bit opcode gives?
   A. xxxx 0000
   B. 1 xxxx 11
   C. 0 xxxx 00
   D. 00 xxxx 0
   Answer: C. 7-bit address. (Key point: Mapping format)

3. On reset CAR loads?
   A. Zero always
   B. SBR
   C. Opcode
   D. Address of the fetch routine
   Answer: D. Starts first microinstruction. (Key point: Initial)

4. Why share routines?
   A. Common routines like indirect calculation are reused
   B. Save ROM speed
   C. Avoid CAR
   D. Avoid status bits
   Answer: A. CALL/RET. (Key point: Subroutine)

## Related in Computer Organization and Architecture

- [Address sequencing for control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-sequencer) — Computer Organization and Architecture, chapter 3, asked 7×
- [Memory-mapped I/O reduces address space](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ammio-address-space) — Computer Organization and Architecture, chapter 7
- [Organization of control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acontrol-memory-org) — Computer Organization and Architecture, chapter 3
- [Control memory vs main memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acontrol-vs-main-memory) — Computer Organization and Architecture, chapter 3

## Related in other subjects

- [Full vs partial address decoding for memory](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Afull-vs-partial-decoding) — Instrumentation II, chapter 2