---
title: "Design of a 2-bit ALU"
subject: "Computer Organization and Architecture"
chapter: 5
key: "semester_5/computer_organization_and_architecture:alu-2bit"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/alu-2bit
site: BCT Engineering
---

# Design of a 2-bit ALU

Computer Organization and Architecture · Chapter 5: Computer Arithmetic

- Asked in: 2071 Shrawan, 3 marks
- Video: [2 Bit ALU (Theory+Practical)](https://www.youtube.com/watch?v=6Nnk5I7XQ7k) — Nusrat Hurain
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/alu-2bit
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-5

## Question

Design a 2-bit ALU that can perform addition, AND and OR operations.

## Short answer

Two 1-bit slices each with AND, OR, full adder and 4×1 MUX. S1S0=00 for AND, 01 for OR, 10 for ADD (carry chain). Slice 0 takes Cin=0, output F0 and carry to slice 1. Common S1,S0 select operation for both bits.

## Answer

A 2-bit ALU is two identical 1-bit slices in cascade. Each slice has a full adder (ADD), an AND gate, an OR gate and a 4×1 multiplexer that selects the result.

| S1 S0 | Operation |
|---|---|
| 0 0 | Fi = Ai AND Bi |
| 0 1 | Fi = Ai OR Bi |
| 1 0 | Fi = Ai + Bi + Ci (add) |
| 1 1 | Not used (spare MUX input) |

```text
   Ai  Bi
    |   |
    +---+------+--------+
    |   |      |        |
 +--v-+ +v---+ +v-------v-+
 | AND| | OR | |Full adder|<-- Ci
 +--+-+ +-+--+ +----+-----+--> Ci+1
    |0    |1        |2
 +--v-----v---------v--+
 |  MUX 4x1 (S1 S0)    |
 +----------+----------+
            v
            Fi
```
- Slice 0: inputs A0, B0, C0 (= 0 for add). Output F0, carry C1.
- Slice 1: inputs A1, B1, C1. Output F1, carry C2 (carry-out).
- Full-adder equations: Sum_i = Ai ⊕ Bi ⊕ Ci, Ci+1 = AiBi + Ci(Ai ⊕ Bi).
- S1 and S0 are common to both slices, so one control word selects the same operation for both bits.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How is the 2-bit ALU built?
   A. One 2-bit adder and a single gate
   B. Two slices with different logic
   C. A decoder only
   D. Two identical 1-bit slices in cascade, each with a full adder, AND, OR and a 4x1 MUX
   Answer: D. Each slice has AND, OR, a full adder and a MUX; two such slices make the 2-bit ALU. (Key point: Slice structure)

2. What does S1 S0 = 01 select in the ALU?
   A. Fi = Ai OR Bi
   B. Fi = Ai AND Bi
   C. Fi = Ai + Bi + Ci
   D. Fi = NOT Ai
   Answer: A. From the table, 00 = AND, 01 = OR, 10 = add. (Key point: Select lines)

3. How are the slices connected for addition?
   A. Carry-out of slice 1 feeds slice 0
   B. Each slice has its own S1 S0
   C. Carry-out C1 of slice 0 feeds carry-in of slice 1, and S1 S0 are common
   D. No carry is passed
   Answer: C. C1 from slice 0 is the carry-in of slice 1; shared S1 S0 select the same operation for both bits. (Key point: Carry connection)

## Related in Computer Organization and Architecture

- [ALU design with 2-bit ALU](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aalu-design) — Computer Organization and Architecture, chapter 5, asked 2×

## Related in other subjects

- [Signed 1's complement addition of (-65)+(+15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aones-complement-addition-8bit) — Digital Logic, chapter 5
- [Design 4-bit R-2R DAC; unipolar vs bipolar](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adesign-4bit-r2r-unipolar-bipolar) — Advanced Electronics, chapter 3
- [Hazards in asynchronous design; 2-bit comparator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahazards-2bit-comparator) — Digital Logic, chapter 4
- [Vector class addition by object argument](https://www.bctengineer.com/question.md?key=semester_3%2Fobject_oriented_programming%3Avector-class-addition) — Object Oriented Programming, chapter 1
