--- title: "ALU design with 2-bit ALU" subject: "Computer Organization and Architecture" chapter: 5 key: "semester_5/computer_organization_and_architecture:alu-design" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/alu-design site: BCT Engineering --- # ALU design with 2-bit ALU Computer Organization and Architecture · Chapter 5: Computer Arithmetic - Asked in: 2075 Chaitra, 8 marks; 2070 Asar, 8 marks (asked 2 times) - Video: [Video 34: Basic ALU Design, CS/ECE 3810 Computer Organization](https://www.youtube.com/watch?v=moGVfZJ31EQ) — Rajeev Balasubramonian - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/alu-design - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-5 ## Question What are the stages of ALU design? Design a 2-bit ALU that can perform addition/subtraction, AND, OR and XOR, explaining with its logic diagram. ## Short answer Stages: specify operations and word length; partition into arithmetic and logic units with a multiplexer; design 1-bit slice with full adder, logic gates, and output selector; cascade slices; verify. A 2-bit ALU uses two such slices with common control lines S1,S0,M. It performs AND, OR, XOR, add, subtract. ## Answer An ALU is a combinational circuit that performs arithmetic and logic microoperations on n-bit operands. It is designed as n identical 1-bit slices connected in cascade. #### Stages of ALU design 1. **Specify** the operations, word length and control inputs (here: add, subtract, AND, OR and XOR on 2 bits). 2. **Partition** the ALU into an arithmetic unit, a logic unit and an output selector (multiplexer). 3. **Design one bit slice**: a full adder with a B-complementer (XOR gate) for add/subtract, AND, OR and XOR gates for the logic unit, and a 4×1 MUX to choose the result. 4. **Cascade** the slices: the carry-out of bit 0 goes to the carry-in of bit 1. Add status flags (carry, zero, sign, overflow). 5. **Verify** the design with a function table and test inputs. #### Function table Select lines S1 S0 and mode M (for arithmetic, M = 0 means add and M = 1 means subtract; the carry-in of bit 0 = M): | S1 S0 | M | Output Fi | |---|---|---| | 0 0 | x | Ai AND Bi | | 0 1 | x | Ai OR Bi | | 1 0 | x | Ai XOR Bi | | 1 1 | 0 | A + B | | 1 1 | 1 | A − B = A + B' + 1 | #### One-bit slice ```text Ai Bi | | | +------------------+ | | | +--------+----+--------+ v | | | | [ XOR ]<--- M v v v | | Bi' = Bi xor M [AND] [OR] [XOR] | Ai v | | | +--> [ Full adder ]<--- Ci | | | | | | | | | Si +---> Ci+1 (to next slice) v v v v +------------------------------------+ | 4 x 1 MUX (select S1 S0) | | 00: AND 01: OR 10: XOR 11: Si | +-----------------+------------------+ v Fi ``` - The AND, OR and XOR gates each take Ai and the original Bi; only the full adder uses Bi'. - Bi' = Bi XOR M, so a subtraction uses the 2's complement of B (B is inverted and C0 = 1). - Sum Si = Ai ⊕ Bi' ⊕ Ci and carry Ci+1 = Ai·Bi' + Ci(Ai ⊕ Bi'). #### 2-bit ALU ```text A1 B1 A0 B0 | | | | +--v--v--+ C1 +--v--v--+ C0 = M | slice 1 |<---------| slice 0 |<--- M +----+----+ +----+----+ | C2 (carry out) | v v F1 F0 (all slices share S1, S0, M) ``` The same S1, S0 and M lines go to both slices. Slice 0 produces F0 and the carry C1; slice 1 uses C1 and produces F1 and the carry-out C2. For example, A = 11 and B = 01 with S1S0 = 11 and M = 0 give F = 00 and C2 = 1 (3 + 1 = 4); with M = 1 they give F = 10 (3 − 1 = 2). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is an n-bit ALU designed? A. As n identical 1-bit slices cascaded B. As one large unit with no slices C. With only a multiplexer D. Using sequential circuit only Answer: A. A one-bit slice is repeated and the carry-out of one feeds the next. (Key point: Bit-slice design) 2. How does the slice subtract? A. XOR B with M and set the first carry-in to M (A + B' + 1) B. Use an AND gate C. Shift B D. Use OR gate Answer: A. Subtraction is addition of the 2's complement of B. (Key point: Add/subtract) 3. What chooses the ALU output in each slice? A. A 4x1 MUX with select lines S1 S0 B. An adder only C. A decoder on M D. The carry Answer: A. 00 AND, 01 OR, 10 XOR, 11 sum/difference. (Key point: Output selection) 4. For A = 11, B = 01 with S1S0 = 11, M = 1, the result is: A. F = 10 (3 - 1 = 2) B. F = 00 with carry C. F = 01 D. F = 11 Answer: A. 3 - 1 = 2 = 10; with M = 0, 3 + 1 = 4 gives F = 00 and carry-out 1. (Key point: Example) ## Related in Computer Organization and Architecture - [Design of a 2-bit ALU](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aalu-2bit) — Computer Organization and Architecture, chapter 5 - [Floating point addition and subtraction](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Afp-add-sub) — Computer Organization and Architecture, chapter 5, asked 6× ## Related in other subjects - [Half adder/subtractor; 1's and 2's complement subtraction](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahalf-adder-subtractor-complement) — Digital Logic, chapter 5 - [Signed 1's complement addition of (-65)+(+15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aones-complement-addition-8bit) — Digital Logic, chapter 5 - [n-bit full adder block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3An-bit-full-adder) — Digital Logic, chapter 5 - [Hazards in asynchronous design; 2-bit comparator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahazards-2bit-comparator) — Digital Logic, chapter 4