--- title: "Arithmetic and instruction pipeline" subject: "Computer Organization and Architecture" chapter: 4 key: "semester_5/computer_organization_and_architecture:arith-instr-pipeline" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/arith-instr-pipeline site: BCT Engineering --- # Arithmetic and instruction pipeline Computer Organization and Architecture · Chapter 4: Pipeline & Vector Processing - Asked in: 2071 Chaitra, 10 marks; 2070 Chaitra, 10 marks (asked 2 times) - Video: [Pipeline Architecture](https://www.youtube.com/watch?v=BSLLDXQTqmM) — Computer Science Lessons - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/arith-instr-pipeline - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-4 ## Question Explain the arithmetic pipeline and instruction pipeline with example. ## Short answer An arithmetic pipeline divides a floating-point add into segments for parallel operation; e.g., X+Y normalised in 4 segments. An instruction pipeline overlaps fetch, decode, operand fetch, and execute of successive instructions; 4 instructions take 7 cycles instead of 16. Both increase throughput by filling pipeline stages simultaneously. ## Answer #### Arithmetic pipeline It splits an arithmetic operation into segments, each done in separate hardware, so a new operation can enter every clock. Example, floating-point addition in four segments: (1) compare exponents, (2) align mantissas, (3) add/subtract mantissas, (4) normalise. ```text X=0.9504x10^3 , Y=0.8200x10^2 1) exponent difference = 1 2) Y -> 0.0820 x 10^3 3) sum = 1.0324 x 10^3 4) normalise -> 0.10324 x 10^4 ``` While pair 1 is being added, pair 2 is being aligned and pair 3 is being compared, giving one result per clock after the first. It is used for vector and scientific processors. #### Instruction pipeline It overlaps the steps of different instructions. A four-segment example: FI (fetch instruction), DA (decode and address calculation), FO (fetch operand), EX (execute). ```text Segment | 1 2 3 4 5 6 7 ------------------------------ FI | I1 I2 I3 I4 . . . DA | . I1 I2 I3 I4 . . FO | . . I1 I2 I3 I4 . EX | . . . I1 I2 I3 I4 ``` For 4 instructions, k + n - 1 = 4 + 4 - 1 = 7 clocks instead of 16. Delays arise from data dependency, branches and resource conflicts, solved by forwarding, stalls, branch prediction and delayed branch. #### Difference | Arithmetic pipeline | Instruction pipeline | |---|---| | Overlaps steps of one arithmetic operation | Overlaps steps of instruction execution | | Stages are arithmetic sub-operations | Stages are fetch, decode, operand fetch, execute | | Used in floating point units, vector machines | Used in all modern CPUs | | Few hazards | Branch, data and structural hazards | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In the four-segment floating-point addition pipeline, what is the correct order of segments? A. Add mantissas, compare exponents, align mantissas, normalise B. Compare exponents, align mantissas, add/subtract mantissas, normalise C. Align mantissas, compare exponents, normalise, add mantissas D. Compare exponents, add mantissas, align mantissas, normalise Answer: B. The exponents are compared first, the smaller number's mantissa is aligned, then the mantissas are added and the result normalised. (Key point: Floating-point addition segments) 2. While pair 1 is being added in an arithmetic pipeline, what happens to the other pairs? A. They wait until pair 1 is completely finished B. Pair 2 is being aligned and pair 3 is being compared at the same time C. They are added in the same segment as pair 1 D. They are stored in memory and processed later Answer: B. Each segment works on a different pair in the same clock, so one result comes out per clock after the first. (Key point: Overlap in arithmetic pipeline) 3. In the four-segment instruction pipeline, which segment fetches the operands from memory? A. FI B. DA C. EX D. FO Answer: D. FO is fetch operand; FI fetches the instruction, DA decodes and calculates the address, and EX executes. (Key point: Instruction pipeline segments) 4. How many clocks do 4 instructions need in a 4-segment pipeline, and why? A. 16, because each instruction takes 4 clocks one after another B. 7, because k + n - 1 = 4 + 4 - 1 C. 8, because k + n = 4 + 4 D. 4, because all instructions run in parallel Answer: B. The first instruction takes k clocks and each remaining one finishes one clock later, giving k + n - 1 = 7 clocks instead of 16. (Key point: Clocks for n instructions) 5. Which of the following is a cause of delay in an instruction pipeline together with a matching solution? A. Data dependency solved by forwarding B. Wide clock solved by branch prediction C. Many registers solved by stalls D. Normalisation solved by delayed branch Answer: A. Delays come from data dependency, branches and resource conflicts; forwarding, stalls, branch prediction and delayed branch are the remedies. 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