---
title: "Associative mapping technique"
subject: "Computer Organization and Architecture"
chapter: 6
key: "semester_5/computer_organization_and_architecture:assoc-mapping-explain"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/assoc-mapping-explain
site: BCT Engineering
---

# Associative mapping technique

Computer Organization and Architecture · Chapter 6: Memory System

- Asked in: 2076 Asoj, 6 marks
- Video: [Associative Mapping](https://www.youtube.com/watch?v=uwnsMaH-iV0) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/assoc-mapping-explain
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-6

## Question

Explain the associative mapping technique.

## Short answer

Associative mapping allows any main memory block to be placed in any cache line. The address is split into tag and word; the tag is compared in parallel with all line tags using content-addressable memory. A match is a hit; on miss, the block is loaded into any free line or replaces a victim chosen by a replacement algorithm. This eliminates thrashing but requires many comparators and a replacement policy.

## Answer

Associative mapping is a cache mapping function in which any block of main memory can be stored in any line of the cache.
A main-memory block can be placed in **any** cache line. The address is split into **Tag | Word**; the tag is the full block number.

```text
   Address (16 bits)
   +----------------------+--------+
   |   Tag  14b          | Word 2b|
   +----------+-----------+--------+
              |
      compare with ALL tags in parallel
   +------+-----------+------+
   | line0| tag0      | data |--= ?
   | line1| tag1      | data |--= ?
   |  ... | ...       | ...  |--= ?
   +------+-----------+------+--> hit / miss
```
Working: the tag is compared with the tags of all lines at the same time (associative or content-addressable memory). A match is a hit. On a miss the block is loaded into any free line; if the cache is full, a **replacement algorithm** (LRU, FIFO, LFU, random) chooses the line to remove.

Example: with 16 lines, blocks 0, 16, 32 and 5 can all stay in the cache together, because any line can hold any block.

- **Merits:** most flexible, best hit ratio, no thrashing.
- **Demerits:** needs one comparator per line (costly, slow, more power), long tag, and a replacement algorithm.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Where can a block go in associative mapping?
   A. Fixed line
   B. Any line
   C. Fixed set
   D. Line 0 only
   Answer: B. Any line. (Key point: Placement)

2. What is the tag?
   A. Line number
   B. Full block number
   C. Word offset
   D. Set number
   Answer: B. Address is Tag | Word. (Key point: Tag)

3. Which is a demerit?
   A. Conflict thrashing
   B. One comparator per line is needed (costly)
   C. Low hit ratio
   D. Fixed placement
   Answer: B. All tags compared in parallel. (Key point: Demerit)

4. When is a replacement algorithm used?
   A. Always on hit
   B. When the cache is full on a miss
   C. Never
   D. On tag compare
   Answer: B. It picks the line to remove. (Key point: Replacement)

## Related in Computer Organization and Architecture

- [Associative mapping and replacement algorithms](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aassociative-mapping) — Computer Organization and Architecture, chapter 6, asked 2×
- [Set associative mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aset-assoc-mapping) — Computer Organization and Architecture, chapter 6
- [Associative cache mapping with example](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aassoc-cache-example) — Computer Organization and Architecture, chapter 6
- [Associative vs set associative mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aassoc-vs-setassoc) — Computer Organization and Architecture, chapter 6
- [Write policy; direct vs associative mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Awp-direct-vs-assoc) — Computer Organization and Architecture, chapter 6
- [Replacement algorithm in associative mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Areplacement-assoc) — Computer Organization and Architecture, chapter 6

## Related in other subjects

- [Associative cache mapping](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aassociative-cache-mapping) — Embedded System, chapter 4, asked 2×
- [Cache memory mapping techniques](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-mapping-techniques) — Embedded System, chapter 4, asked 3×
- [Compaction vs coalescing; paging mapping](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Acompaction-coalescing-paging) — Operating System, chapter 4