---
title: "Bus interconnection"
subject: "Computer Organization and Architecture"
chapter: 1
key: "semester_5/computer_organization_and_architecture:bus-interconnection"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/bus-interconnection
site: BCT Engineering
---

# Bus interconnection

Computer Organization and Architecture · Chapter 1: Introduction

- Asked in: 2071 Shrawan, 2 marks; 2069 Chaitra, 3 marks (asked 2 times)
- Video: [22 bus interconnection](https://www.youtube.com/watch?v=Qtg4YY4F1GI) — OU Education
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/bus-interconnection
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-1

## Question

What do you mean by bus interconnection?

## Short answer

Bus interconnection connects CPU, memory, and I/O modules via shared data, address, and control lines. The data bus carries data/instructions, the address bus selects memory/I/O locations, and the control bus carries timing and command signals. Only one device transmits at a time.

## Answer

A bus is a shared communication path of one or more wires that carries information between two or more devices. Bus interconnection means connecting the CPU, memory and I/O modules by buses so that they can exchange data, addresses and control signals.

A system bus has three groups of lines:
- **Data bus:** carries data and instructions. Its width (8, 16, 32, 64 bits) decides how much data moves in one transfer.
- **Address bus:** carries the address of the memory location or I/O port being used. Its width decides the maximum memory: 2ⁿ locations for n lines.
- **Control bus:** carries timing and command signals, such as Memory Read/Write, I/O Read/Write, Bus Request/Grant, Interrupt Request/Acknowledge, Clock and Reset.

```text
 +-----+   +--------+   +------+
 | CPU |   | Memory |   | I/O  |
 +--+--+   +---+----+   +--+---+
    |          |           |
 ===+==========+===========+=== Address bus
 ===+==========+===========+=== Data bus
 ===+==========+===========+=== Control bus
```

Only one device may transmit on the bus at a time; others listen. The advantages are low cost and easy addition of devices. The disadvantage is that the shared bus can become a bottleneck.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is a bus?
   A. A dedicated link between exactly two devices
   B. A memory chip
   C. A shared communication path of one or more wires between two or more devices
   D. A part of the ALU
   Answer: C. A bus is shared; this is why only one device can transmit at a time. (Key point: Bus definition)

2. A system has n address lines. How many locations can it address?
   A. 2^n
   B. n^2
   C. 2n
   D. n
   Answer: A. Each line carries one bit, giving 2^n distinct addresses. (Key point: Address bus width)

3. Which signals travel on the control bus?
   A. Only data bytes
   B. Only memory addresses
   C. Memory Read/Write, interrupt request, clock, reset
   D. Only instructions
   Answer: C. The control bus carries timing and command signals. (Key point: Control bus)

## Related in Computer Organization and Architecture

- [Interconnection structure of computer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ainterconnection-structure) — Computer Organization and Architecture, chapter 1, asked 3×

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