---
title: "Bus structure of a typical computer"
subject: "Computer Organization and Architecture"
chapter: 1
key: "semester_5/computer_organization_and_architecture:bus-structure"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/bus-structure
site: BCT Engineering
---

# Bus structure of a typical computer

Computer Organization and Architecture · Chapter 1: Introduction

- Asked in: 2078 Kartik, 4 marks
- Video: [L-1.4:Types of Buses (Address, Data and Control) in Computer Organization and Architecture](https://www.youtube.com/watch?v=xBYhHC8_A6o) — Gate Smashers
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/bus-structure
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-1

## Question

Compare and explain the bus structure of a typical computer system.

## Short answer

A typical system bus has address, data, and control lines connecting CPU, memory, and I/O. Single-bus designs are simple but slow; dual-bus separates memory and I/O for concurrency; a bus hierarchy with local, system, and expansion buses offers the best performance by matching bus speeds to device needs.

## Answer

The bus structure of a typical computer uses a **system bus** that joins the CPU, main memory and I/O modules. It has three groups of lines.

```text
 +-----+   +--------+   +--------+   +--------+
 | CPU |   | Memory |   | I/O 1  |   | I/O 2  |
 +--+--+   +---+----+   +---+----+   +---+----+
    |          |            |            |
 ===+==========+============+============+== Address bus
 ===+==========+============+============+== Data bus
 ===+==========+============+============+== Control bus
```

| Bus | Direction | Function |
|---|---|---|
| Address bus | One way, CPU to others | Selects memory location or I/O port; width decides memory size |
| Data bus | Two way | Carries data and instructions; width decides word moved per transfer |
| Control bus | Both ways | Carries Read/Write, interrupt, bus request/grant, clock, reset |

Comparison of the common structures:
- **Single bus:** all devices share one bus. Cheap and simple, but slow when busy.
- **Dual or multiple bus:** a separate memory bus (CPU and memory) and I/O bus (peripherals). The CPU can use memory while I/O runs. Faster but costlier.
- **Bus hierarchy:** local, system and expansion buses with bridges. Best performance and used in modern PCs.

Only one device drives the bus at one time, so arbitration is needed.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What decides the memory size in a bus structure?
   A. Address bus width
   B. Data bus width
   C. Control bus width
   D. Clock
   Answer: A. Width of the address bus decides the number of locations. (Key point: Address bus)

2. Why is a dual or multiple bus faster than a single bus?
   A. It has only one bus
   B. It removes arbitration
   C. CPU can use memory while I/O runs on a separate bus
   D. It has fewer devices
   Answer: C. Separate memory and I/O buses allow concurrency. (Key point: Dual bus advantage)

3. Which bus is bidirectional and carries Read/Write, interrupt and clock?
   A. Control bus
   B. Address bus only
   C. None
   D. Local bus only
   Answer: A. The control bus carries signals in both directions. (Key point: Control bus direction)

## Related in Computer Organization and Architecture

- [Interconnection structure of computer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ainterconnection-structure) — Computer Organization and Architecture, chapter 1, asked 3×
- [Limitations of single bus system](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Asingle-bus-limit) — Computer Organization and Architecture, chapter 1, asked 2×
- [Types of bus arbitration](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Abus-arbitration) — Computer Organization and Architecture, chapter 1
- [Data bus and address bus width](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Abus-widths) — Computer Organization and Architecture, chapter 1, asked 2×
- [Bus interconnection](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Abus-interconnection) — Computer Organization and Architecture, chapter 1, asked 2×
- [Performance balance and bus design elements](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aperf-balance-bus-design) — Computer Organization and Architecture, chapter 1, asked 2×

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