---
title: "Data bus and address bus width"
subject: "Computer Organization and Architecture"
chapter: 1
key: "semester_5/computer_organization_and_architecture:bus-widths"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/bus-widths
site: BCT Engineering
---

# Data bus and address bus width

Computer Organization and Architecture · Chapter 1: Introduction

- Asked in: 2075 Chaitra, 2 marks; 2071 Chaitra, 2 marks (asked 2 times)
- Video: [Address, Data and Control Buses](https://www.youtube.com/watch?v=3osm-soT_Lc) — MrBrownCS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/bus-widths
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-1

## Question

What does the width of the data bus / address bus represent in a system?

## Short answer

Data bus width is the number of bits transferred per cycle, determining data transfer size and performance. Address bus width is the number of address lines, defining the maximum directly addressable memory (2^n locations). For example, 32 address lines yield 4 GB.

## Answer

#### Data bus width
The data bus width is the number of bits that can be transferred between the CPU and memory or I/O in one bus cycle. It decides the amount of data moved per transfer and so affects performance. A 32-bit data bus moves 4 bytes at a time; a 64-bit bus moves 8 bytes. It usually matches the word size of the processor.

#### Address bus width
The address bus width is the number of address lines. It decides the maximum number of memory locations the CPU can directly address, which is 2ⁿ for n lines.
- 16 lines: 2¹⁶ = 64 K locations (8085)
- 20 lines: 2²⁰ = 1 MB (8086)
- 32 lines: 2³² = 4 GB

The address bus is unidirectional (CPU to memory), while the data bus is bidirectional.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does the data bus width represent?
   A. The maximum memory size
   B. Number of bits transferred in one bus cycle
   C. The number of devices on the bus
   D. The clock frequency
   Answer: B. A 32-bit bus moves 4 bytes per transfer. (Key point: Data bus width)

2. How much memory can a CPU with 20 address lines address?
   A. 64 KB
   B. 4 GB
   C. 20 MB
   D. 1 MB
   Answer: D. 2^20 = 1 MB (as in the 8086). (Key point: Address bus size)

3. Which statement about bus direction is correct?
   A. Address bus is bidirectional; data bus is unidirectional
   B. Address bus is unidirectional; data bus is bidirectional
   C. Both are unidirectional
   D. Both are bidirectional
   Answer: B. Addresses go from CPU to memory only, while data can go both ways. (Key point: Direction)

## Related in Computer Organization and Architecture

- [Limitations of single bus system](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Asingle-bus-limit) — Computer Organization and Architecture, chapter 1, asked 2×
- [Bus structure of a typical computer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Abus-structure) — Computer Organization and Architecture, chapter 1

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