---
title: "Elements of cache design"
subject: "Computer Organization and Architecture"
chapter: 6
key: "semester_5/computer_organization_and_architecture:cache-design-elements"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/cache-design-elements
site: BCT Engineering
---

# Elements of cache design

Computer Organization and Architecture · Chapter 6: Memory System

- Asked in: 2075 Asoj, 4 marks
- Video: [Cache Design - An Overview](https://www.youtube.com/watch?v=1tvW8kzOpSA) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/cache-design-elements
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-6

## Question

Explain the various types of elements of cache design.

## Short answer

Cache design involves cache size (balance speed and hit ratio), mapping function (direct, associative, set-associative), replacement algorithm (LRU, FIFO, etc.), write policy (write-through or write-back), line size (typically 8–64 bytes), number of caches (L1, L2, split/unified), and address type (logical or physical).

## Answer

The main elements (design parameters) of cache design are:

1. **Cache size:** small enough for low cost and fast access, large enough for a high hit ratio.
2. **Mapping function:** direct, associative or set associative; decides where a block may be placed.
3. **Replacement algorithm:** LRU, FIFO, LFU or random; chooses the block to remove when the cache or set is full.
4. **Write policy:** write-through, write-back or write-once; decides when main memory is updated.
5. **Line (block) size:** larger lines exploit spatial locality but fewer lines fit and the miss penalty rises; typical sizes are 8 to 64 bytes.
6. **Number of caches:** multilevel (L1, L2, L3) and unified or split (separate instruction and data) caches.
7. **Cache addresses:** logical (virtual) cache or physical cache, depending on whether it sits before or after the MMU.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which is NOT a cache design element?
   A. Cache size
   B. Write policy
   C. Mapping function
   D. Bus clock of the printer
   Answer: D. Elements: size, mapping, replacement, write policy, line size, number of caches, addresses. (Key point: Elements)

2. Effect of larger lines?
   A. Exploit spatial locality but fewer lines fit and miss penalty rises
   B. Always lower hit ratio
   C. No effect
   D. Remove tags
   Answer: A. There is a trade-off. (Key point: Line size)

3. Split cache means?
   A. Separate instruction and data caches
   B. Two copies of memory
   C. Cache in two cities
   D. L3 only
   Answer: A. Unified vs split. (Key point: Number of caches)

4. Logical cache sits?
   A. After MMU
   B. Before the MMU using virtual addresses
   C. In memory
   D. On disk
   Answer: B. Logical (virtual) cache is before the MMU. (Key point: Cache addresses)

## Related in Computer Organization and Architecture

- [Performance balance and bus design elements](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aperf-balance-bus-design) — Computer Organization and Architecture, chapter 1, asked 2×
- [Cache read and direct-mapping demerits](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-demerits) — Computer Organization and Architecture, chapter 6

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