---
title: "Cache organization"
subject: "Computer Organization and Architecture"
chapter: 6
key: "semester_5/computer_organization_and_architecture:cache-organization"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/cache-organization
site: BCT Engineering
---

# Cache organization

Computer Organization and Architecture · Chapter 6: Memory System

- Asked in: 2071 Chaitra, 4 marks
- Video: [L-3.5: What is Cache Mapping || Cache Mapping techniques || Computer Organisation and Architecture](https://www.youtube.com/watch?v=m1dA7D6c3C0) — Gate Smashers
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/cache-organization
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-6

## Question

Explain cache organization.

## Short answer

Cache organization includes data memory for blocks, tag memory with valid and dirty bits, comparators for parallel tag comparison, and a controller for hit/miss logic, replacement, and write policy. The address is split into Tag, Line/Set, and Word fields. On a read hit, the word is sent to the CPU; on a miss, the block is fetched from main memory.

## Answer

Cache organization describes how the cache is arranged and connected so that it can store blocks and find them quickly.

```text
   CPU <----> +------------------------------+ <----> Main
              |        CACHE                 |        memory
   address -->| Controller (hit/miss logic)  |
              |  +--------+  +------------+  |
              |  | Tag    |  | Data       |  |
              |  | memory |  | memory     |  |
              |  |V|D|tag |  | block data |  |
              |  +---+----+  +------+-----+  |
              |      v              |        |
              |  Comparator ----> hit/miss   |
              +------------------------------+
```
- **Data memory:** stores blocks (lines) copied from main memory; one line holds several words.
- **Tag memory:** stores the tag (high-order address bits) of each line, plus a **valid bit** and a **dirty bit** (for write-back).
- **Comparator:** compares the address tag with the stored tag; a match with the valid bit set is a hit.
- **Controller:** controls the read/write, block fetch on a miss, replacement and write policy.
- **Mapping:** direct, associative or set associative decides where a block may be placed.
- **Address split:** Tag | Line (or Set) | Word; the word field selects a word in the line.

On a **read hit** the word goes to the CPU; on a **read miss** the whole block is fetched from main memory and the word is forwarded to the CPU.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does the tag memory store?
   A. Block data
   B. Tag of each line plus valid and dirty bits
   C. Only the replacement algorithm
   D. CPU registers
   Answer: B. Tag memory holds high-order address bits and the status bits. (Key point: Tag memory)

2. When is an access a hit?
   A. Tags match and the valid bit is set
   B. Tags differ
   C. Dirty bit is set
   D. Cache is full
   Answer: A. The comparator must find a tag match with valid bit set. (Key point: Hit condition)

3. What happens on a read miss?
   A. Only the requested word is fetched and nothing stored
   B. The whole block is fetched from main memory and the word is forwarded to the CPU
   C. The CPU halts permanently
   D. The block is fetched from the disk
   Answer: B. A whole block is brought in, not a single word. (Key point: Read miss)

4. Which component handles block fetch, replacement and write policy?
   A. Comparator
   B. Data memory
   C. Cache controller
   D. Tag memory
   Answer: C. The controller manages read/write, fetch on miss, replacement and write policy. (Key point: Controller role)

## Related in Computer Organization and Architecture

- [Cache mapping techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acache-mapping-techniques) — Computer Organization and Architecture, chapter 6, asked 7×
- [Direct cache mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping) — Computer Organization and Architecture, chapter 6, asked 3×
- [Direct mapping with 32-block memory, 8-block cache](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example) — Computer Organization and Architecture, chapter 6, asked 3×
- [Cache write policy techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Awrite-policy) — Computer Organization and Architecture, chapter 6
- [Associative cache mapping with example](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aassoc-cache-example) — Computer Organization and Architecture, chapter 6
- [Cache read and direct-mapping demerits](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-demerits) — Computer Organization and Architecture, chapter 6