---
title: "CPU and IOP communication"
subject: "Computer Organization and Architecture"
chapter: 7
key: "semester_5/computer_organization_and_architecture:cpu-iop-communication"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/cpu-iop-communication
site: BCT Engineering
---

# CPU and IOP communication

Computer Organization and Architecture · Chapter 7: Input-Output Organization

- Asked in: 2075 Asoj, 7 marks; 2072 Kartik, 6 marks (asked 2 times)
- Video: [Input output processor // CPU and IOP operations](https://www.youtube.com/watch?v=ocWMD0yurO0) — Yachana Bhawsar
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/cpu-iop-communication
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-7

## Question

Explain the communication between CPU and IOP with necessary block diagram.

## Short answer

The CPU tests the IOP’s status, then sends a start I/O command with the I/O program address before resuming its own work. The IOP independently fetches and executes the I/O program, transferring data directly to/from memory, and interrupts the CPU only when the operation completes.

## Answer

The CPU and the IOP communicate through memory and a few control instructions. The CPU does not execute the I/O; it only starts an I/O program and the IOP runs it.

#### Block diagram

```text
        +---------+          +-------------------+
        | Memory  |<-------->|   Memory bus      |
        |  unit   |          +----+---------+----+
        +---------+               |         |
                              +---v---+  +--v----+
                              |  CPU  |  |  IOP  |
                              +-------+  +--+----+
                                            | I/O bus
                          +---------+-------+---------+
                          v         v                 v
                      Keyboard    Printer           Disk
                                  (peripherals)
```

#### Sequence of communication

```text
   CPU                             IOP
    | -- test IOP path ----------> |
    | <-- status (ready/busy) ---- |
    | -- start I/O (device,        |
    |    address of program) ----> |
    |   (CPU continues own work)   | fetch I/O program
    |                              | from memory (DMA)
    |                              | transfer data
    | <-- interrupt -------------- | (transfer done)
    | -- read status word -------> |
    | <-- status ----------------- |
    | -- check status, error? ---- |
```

1. The CPU sends an instruction to **test the IOP path** to see if the IOP is ready. The IOP replies with a status word (ready or busy, errors).
2. If the IOP is ready, the CPU sends the **start I/O** instruction with the device address and the address of the I/O program (a list of commands) in memory. The CPU then continues its own program.
3. The IOP fetches the I/O program from memory, interprets the commands (read or write, block size, memory address) and transfers data directly with the memory by cycle stealing, controlling the device through the interface.
4. When the transfer is complete, or on an error, the IOP sends an **interrupt** to the CPU.
5. The CPU responds by reading the IOP status word from memory and checking whether the transfer was good, and then continues or starts another I/O.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Who runs the I/O program in CPU-IOP communication?
   A. The memory unit runs it
   B. The IOP runs it, while the CPU only starts it
   C. The peripheral device runs it
   D. The CPU executes it step by step
   Answer: B. The CPU only starts an I/O program in memory; the IOP fetches and executes it. (Key point: Role of the IOP)

2. Why does the CPU first send a 'test IOP path' instruction?
   A. To check whether the IOP is ready or busy before starting I/O
   B. To clear the interrupt
   C. To load the I/O program into memory
   D. To start the data transfer
   Answer: A. The IOP replies with a status word (ready/busy, errors) and the CPU starts I/O only if it is ready. (Key point: Test IOP path)

3. What does the CPU give the IOP with the 'start I/O' instruction?
   A. The interrupt vector table
   B. The word count register contents only
   C. The device address and the memory address of the I/O program
   D. The data to be transferred
   Answer: C. The IOP needs to know which device and where the I/O program (command list) is in memory. (Key point: Start I/O information)

4. How does the IOP tell the CPU that the transfer is complete, and what does the CPU then do?
   A. It sends an interrupt; the CPU reads the IOP status word from memory and checks for errors
   B. It sends no signal; the CPU polls memory forever
   C. It stops the CPU; the CPU reloads the program
   D. It sets a jumper; the CPU reboots
   Answer: A. On completion or error the IOP interrupts the CPU, which reads the status word and checks whether the transfer was good. (Key point: Completion)

## Related in Computer Organization and Architecture

- [Need for I/O processor (IOP)](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Awhy-iop) — Computer Organization and Architecture, chapter 7, asked 5×
- [DMA controller block diagram and transfer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-controller) — Computer Organization and Architecture, chapter 7, asked 6×
- [Need for IOP and DMA control](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Awhy-iop-dma) — Computer Organization and Architecture, chapter 7
- [Hardwired vs microprogrammed; sequencer diagram](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ahardwired-vs-micro-sequencer) — Computer Organization and Architecture, chapter 3

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