--- title: "General register organization in CPU" subject: "Computer Organization and Architecture" chapter: 2 key: "semester_5/computer_organization_and_architecture:cpu-register-org" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/cpu-register-org site: BCT Engineering --- # General register organization in CPU Computer Organization and Architecture · Chapter 2: Central Processing Unit - Asked in: 2071 Chaitra, 6 marks - Video: [General register Organization | COA | Lec-22 | Bhanu Priya](https://www.youtube.com/watch?v=vjqnWn5PdD0) — Education 4u - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/cpu-register-org - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-2 ## Question Explain the general organization of registers in the CPU. ## Short answer A CPU register file connects to the ALU via two multiplexers (SELA, SELB) for operand selection and a decoder (SELD) for destination loading. A 14-bit control word (3+3+3+5 bits) specifies SELA, SELB, SELD, and OPR for one micro-operation per cycle. Additional registers include PC, IR, MAR, MBR, AC, PSW, stack pointer, and index registers. This organization reduces memory accesses, speeds execution, and shortens instructions. ## Answer A CPU contains a set of registers to hold data and addresses, so that the ALU does not need to access memory for every operand. In the general register organization, a bank of registers is connected to the ALU through multiplexers and buses. ```text +-----------------------------+ Clock -->| R1 R2 R3 R4 R5 R6 R7 |<-- Load <-- [3x8 decoder] <-- SELD +-----------------------------+ | (7 register outputs | | + external input) | SELA --> [ MUX A ] [ MUX B ] <-- SELB | A bus | B bus +------> [ ALU ] <----+ ^ | OPR ---+ +--> Output (fed back to the register inputs) ``` #### Parts - **Register file (R1–R7):** general-purpose registers. - **Two multiplexers (MUX A and MUX B):** select the source registers for the two ALU inputs. They are controlled by SELA and SELB. - **ALU:** performs the operation chosen by the OPR field. - **Decoder (SELD):** enables loading of the destination register that receives the result. - **Input / output:** the external input can be selected by a multiplexer and loaded into a register; the ALU result can be sent out. #### Control word A 14-bit control word selects one micro-operation: SELA (3), SELB (3), SELD (3), OPR (5). For R1 ← R2 + R3: SELA = R2 (010), SELB = R3 (011), SELD = R1 (001), OPR = ADD (00010), so the control word is 010 011 001 00010. The operation completes in one clock cycle. #### Other registers in a CPU PC (next instruction address), IR (current instruction), AR/MAR, DR/MBR, AC, status flags (PSW), stack pointer and index registers. Advantages: fewer memory accesses, faster programs, and shorter instructions because register addresses need only a few bits. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the job of MUX A and MUX B in the general register organization? A. To select the destination register B. To select the ALU operation C. To select the source registers for the two ALU inputs D. To store the result of the ALU Answer: C. SELA and SELB drive the two multiplexers, which choose the registers feeding the ALU. (Key point: Role of multiplexers) 2. What does the SELD decoder do? A. It selects the first ALU operand B. It enables loading of the destination register that receives the result C. It chooses the ALU opcode D. It fetches the next instruction Answer: B. The 3x8 decoder activates the load input of only the destination register. (Key point: Role of SELD decoder) 3. How many bits are in the control word and how is it divided? A. 14 bits: SELA 3, SELB 3, SELD 3, OPR 5 B. 12 bits: SELA 3, SELB 3, SELD 3, OPR 3 C. 16 bits: SELA 4, SELB 4, SELD 4, OPR 4 D. 11 bits: SELA 3, SELB 3, SELD 3, OPR 2 Answer: A. Three 3-bit register selectors plus a 5-bit operation field make 14 bits. (Key point: Control word size) 4. For R1 <- R2 + R3, which fields are set? A. SELA = R1, SELB = R2, SELD = R3, OPR = ADD B. SELA = R2, SELB = R3, SELD = R3, OPR = ADD C. SELA = R3, SELB = R2, SELD = R2, OPR = ADD D. SELA = R2, SELB = R3, SELD = R1, OPR = ADD Answer: D. The sources go through the multiplexers and the destination is picked by SELD; the operation completes in one clock cycle. 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