---
title: "Data dependency problem in pipelining"
subject: "Computer Organization and Architecture"
chapter: 4
key: "semester_5/computer_organization_and_architecture:data-dependency"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/data-dependency
site: BCT Engineering
---

# Data dependency problem in pipelining

Computer Organization and Architecture · Chapter 4: Pipeline & Vector Processing

- Asked in: 2075 Chaitra, 5 marks
- Video: [Data Hazards in Pipelining: Pipelining Hazards and Case Studies | COA](https://www.youtube.com/watch?v=3bkgwvfQSNQ) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/data-dependency
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-4

## Question

Discuss in detail the data dependency problem that arises in pipelining along with its solution.

## Short answer

A data hazard (RAW) occurs when an instruction needs an operand not yet written by an earlier instruction. Solutions include hardware interlocking (stall), operand forwarding (bypassing) to supply data early, compiler scheduling of instructions, and register renaming to eliminate false dependencies.

## Answer

Data dependency (data hazard) occurs when an instruction needs the result of a previous instruction which is still in the pipeline and has not yet been written back. If the pipeline goes on, the later instruction would read an old value.

Example:
```text
 I1: ADD R1, R2, R3     ; R1 = R2 + R3  (result in EX)
 I2: SUB R4, R1, R5     ; needs new R1 in operand fetch
```
Types: **RAW** (read after write, true dependency), **WAR** (write after read) and **WAW** (write after write), the last two arising when instructions complete out of order.

Effect: without correction, I2 reads the old R1 and gives a wrong result. The pipeline must stall or the value be supplied early, which reduces speedup.

#### Solutions
1. **Hardware interlock:** a circuit detects the dependency and holds the later instruction (inserts a bubble) until the result is ready.
2. **Operand forwarding (bypassing):** the ALU result is sent straight to the ALU input of the next instruction through extra paths and multiplexers, without waiting for the register write.
3. **Compiler (software) scheduling / delayed load:** the compiler inserts NOP instructions or reorders independent instructions between the dependent ones.
4. **Register renaming** to remove WAR and WAW dependencies.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What causes a data hazard?
   A. An instruction needs the result of an earlier one that is not yet written back
   B. Two instructions are the same
   C. The clock is too slow
   D. Memory is full
   Answer: A. The later instruction would read an old value if the pipeline simply continued. (Key point: Meaning of data dependency)

2. Which type is the true dependency?
   A. WAR
   B. WAW
   C. RAW
   D. RAR
   Answer: C. RAW (read after write) is the true dependency; WAR and WAW arise with out-of-order completion. (Key point: Types)

3. What does operand forwarding do?
   A. Sends the ALU result straight to the next instruction's ALU input without waiting for the register write
   B. Stops the pipeline until write back
   C. Deletes the dependent instruction
   D. Renames memory
   Answer: A. Extra paths and multiplexers bypass the register file. (Key point: Operand forwarding)

4. What does a hardware interlock do?
   A. Detects dependency and holds the later instruction by inserting a bubble
   B. Predicts the branch
   C. Reorders instructions at compile time
   D. Copies the register file
   Answer: A. The stall continues until the result is ready. (Key point: Hardware interlock)

5. Register renaming removes which dependencies?
   A. RAW
   B. WAR and WAW
   C. All structural hazards
   D. Control hazards
   Answer: B. Renaming gives separate registers, removing false dependencies. (Key point: Register renaming)

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