--- title: "Direct cache mapping" subject: "Computer Organization and Architecture" chapter: 6 key: "semester_5/computer_organization_and_architecture:direct-mapping" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/direct-mapping site: BCT Engineering --- # Direct cache mapping Computer Organization and Architecture · Chapter 6: Memory System - Asked in: 2076 Chaitra, 4 marks; 2072 Chaitra, 6 marks; 2071 Shrawan, 6 marks (asked 3 times) - Video: [Direct Memory Mapping](https://www.youtube.com/watch?v=V_QS1HzJ8Bc) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/direct-mapping - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-6 ## Question Explain direct cache mapping technique with organization diagram, example, merits and demerits. ## Short answer Direct mapping places each main memory block into exactly one cache line: line = block mod number of lines. Address splits into tag, line, and word. It is simple and fast but fixed mapping can cause thrashing when blocks compete for the same line. ## Answer Cache memory is a small, very fast memory placed between the CPU and main memory. It holds copies of the most recently used blocks of main memory, so that most CPU accesses are served at cache speed. It works because of locality of reference (temporal and spatial). Example system used below: main memory = 64K words (16-bit address), block size = 4 words, cache = 16 lines (64 words). Main memory has 16384 blocks. #### Direct mapping Each main-memory block can go to exactly one cache line: line number = (block number) mod (number of lines). The address is split into **Tag | Line | Word**. ```text Address (16 bits) +-----------+---------+--------+ | Tag 10b | Line 4b | Word 2b| +-----+-----+----+----+--------+ | | | +-----v------+ | | line 0 | tag | data | | line 1 | tag | data | | ... | | | line 15 | tag | data | +-----+------+ v v +--------------------+ | compare tag = ? |--> hit / miss +--------------------+ ``` Working: the line field selects one line, and the tag stored there is compared with the tag of the address. If the tags are equal (and the valid bit is set), it is a **hit**, and the word field picks the word. Otherwise it is a **miss**: the block is read from memory into that line, and the line's tag is updated. Example: blocks 0, 16, 32 of main memory all map to line 0 (block mod 16); block 5 maps to line 5; block 21 also maps to line 5. - **Merits:** simple and cheap hardware (only one comparator), fast lookup, no replacement algorithm needed. - **Demerits:** fixed location for each block, so two blocks that map to the same line keep replacing each other (thrashing) even when other lines are empty; lower hit ratio. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is a hit detected in direct mapping? A. All tags are compared in parallel B. The line field selects a line and its tag equals the address tag (valid bit set) C. Any matching word counts D. The set tag matches Answer: B. Only one comparison is needed. (Key point: Hit test) 2. What is the main demerit? A. Blocks mapping to the same line keep replacing each other (thrashing) B. Needs a replacement algorithm C. Needs a comparator per line D. Cannot store data Answer: A. Fixed placement causes conflicts even when other lines are empty. (Key point: Demerit) 3. Why is no replacement algorithm needed? A. Cache is never full B. Blocks are never replaced C. Each block has only one possible line D. Random choice is used Answer: C. There is no choice to make. (Key point: Replacement) ## Related in Computer Organization and Architecture - [Cache read and direct-mapping demerits](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-demerits) — Computer Organization and Architecture, chapter 6 - [Direct mapping with 32-block memory, 8-block cache](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example) — Computer Organization and Architecture, chapter 6, asked 3× - [Direct mapping with 32-block memory, 10 blocks used](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example-10) — Computer Organization and Architecture, chapter 6, asked 3× - [Direct mapping with 64-block memory, 10 blocks used](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example-64) — Computer Organization and Architecture, chapter 6, asked 3× - [Cache mapping techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acache-mapping-techniques) — Computer Organization and Architecture, chapter 6, asked 7× - [Cache management; direct vs associative address structure](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-vs-assoc-address) — Computer Organization and Architecture, chapter 6 ## Related in other subjects - [Associative cache mapping](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aassociative-cache-mapping) — Embedded System, chapter 4, asked 2× - [Cache memory mapping techniques](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-mapping-techniques) — Embedded System, chapter 4, asked 3× - [Reactors in stations: merits and demerits](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_plant_equipment%3Areactors-merits-demerits) — Power Plant Equipment, chapter 4 - [Cofferdam types, uses, merits and demerits](https://www.bctengineer.com/question.md?key=semester_5%2Ffoundation_engineering%3Acofferdam-types-merits) — Foundation Engineering, chapter 5, asked 7×