--- title: "Cache read and direct-mapping demerits" subject: "Computer Organization and Architecture" chapter: 6 key: "semester_5/computer_organization_and_architecture:direct-mapping-demerits" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/direct-mapping-demerits site: BCT Engineering --- # Cache read and direct-mapping demerits Computer Organization and Architecture · Chapter 6: Memory System - Asked in: 2068 Chaitra, 8 marks - Video: [Direct Memory Mapping](https://www.youtube.com/watch?v=V_QS1HzJ8Bc) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/direct-mapping-demerits - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-6 ## Question Explain the cache read operation. What are the demerits of the direct mapping technique used in cache design? Describe in detail any one of the mapping techniques that solves these problems. ## Short answer Cache read splits address into tag, line, and word; tag comparison yields hit (word from cache) or miss (block fetched from memory). Direct mapping forces each block to one fixed line, causing thrashing and conflict misses when multiple blocks map to the same line, lowering hit ratio and leaving other lines unused. Associative mapping solves this by allowing any block in any line, using parallel tag comparison and a replacement algorithm. ## Answer #### Cache read operation ```text CPU gives address | Is block in cache? (tag compare) /Yes \No Hit: fetch word Miss: read block from main memory from cache and load it into a cache line | (replace a line if needed) | Deliver the word to the CPU v v Word delivered to CPU ``` The address is split into tag, line/set and word fields. The cache is checked first; on a hit the word is returned at cache speed, on a miss the whole block is brought from main memory (the word may be sent to the CPU as soon as it arrives) and the tag is updated. #### Demerits of direct mapping - Each block has only one possible line, so blocks that map to the same line keep evicting each other (thrashing), even when other lines are empty. - This gives conflict misses and a lower hit ratio, for example when a loop alternates between two blocks whose numbers differ by a multiple of the number of lines. - Cache usage is not uniform, since some lines are used heavily and others hardly at all. #### Associative mapping solves these problems ```text Address (16 bits) +----------------------+--------+ | Tag 14b | Word 2b| +----------+-----------+--------+ | compare with ALL tags in parallel +------+-----------+------+ | line0| tag0 | data |--= ? | line1| tag1 | data |--= ? | ... | ... | ... |--= ? +------+-----------+------+--> hit / miss ``` Working: the tag is compared with the tags of all lines at the same time (associative or content-addressable memory). A match is a hit. On a miss the block is loaded into any free line; if the cache is full, a **replacement algorithm** (LRU, FIFO, LFU, random) chooses the line to remove. Example: with 16 lines, blocks 0, 16, 32 and 5 can all stay in the cache together, because any line can hold any block. - **Merits:** most flexible, best hit ratio, no thrashing. - **Demerits:** needs one comparator per line (costly, slow, more power), long tag, and a replacement algorithm. Associative mapping removes thrashing because a block may use any free line. Set associative mapping gives a similar benefit at lower cost. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. On a cache read miss what is done? A. Only the word is read B. The block is read from main memory into a cache line and tag updated C. The CPU is interrupted D. The cache is cleared Answer: B. The whole block is loaded and the tag updated. (Key point: Read operation) 2. What is the main demerit of direct mapping? A. Needs many comparators B. Blocks mapping to the same line keep evicting each other even if other lines are empty C. Needs replacement algorithm D. Long tag Answer: B. Fixed placement causes conflict misses. (Key point: Thrashing) 3. What does direct mapping do to cache usage? A. Uniform usage B. Some lines used heavily, others hardly C. All lines unused D. Only set 0 used Answer: B. Cache usage is not uniform. (Key point: Uneven usage) 4. Why does associative mapping solve thrashing? A. Blocks can use any free line B. It removes the tag C. It has no cache D. It uses one line Answer: A. Any block can be placed in any line, so conflicting blocks coexist. (Key point: Solution) ## Related in Computer Organization and Architecture - [Direct cache mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping) — Computer Organization and Architecture, chapter 6, asked 3× - [Direct mapping with 32-block memory, 10 blocks used](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example-10) — Computer Organization and Architecture, chapter 6, asked 3× - [Direct mapping with 64-block memory, 10 blocks used](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example-64) — Computer Organization and Architecture, chapter 6, asked 3× - [Direct mapping with 32-block memory, 8-block cache](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example) — Computer Organization and Architecture, chapter 6, asked 3× - [Cache mapping techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acache-mapping-techniques) — Computer Organization and Architecture, chapter 6, asked 7× - [Write policy; direct vs associative mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Awp-direct-vs-assoc) — Computer Organization and Architecture, chapter 6 ## Related in other subjects - [Cache memory mapping techniques](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-mapping-techniques) — Embedded System, chapter 4, asked 3× - [Associative cache mapping](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aassociative-cache-mapping) — Embedded System, chapter 4, asked 2× - [Cache write techniques](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-write-techniques) — Embedded System, chapter 4 - [Multiplexing techniques; analog one explained](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Alist-mux-techniques) — Data Communication, chapter 6