---
title: "Cache management; direct vs associative address structure"
subject: "Computer Organization and Architecture"
chapter: 6
key: "semester_5/computer_organization_and_architecture:direct-vs-assoc-address"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/direct-vs-assoc-address
site: BCT Engineering
---

# Cache management; direct vs associative address structure

Computer Organization and Architecture · Chapter 6: Memory System

- Asked in: 2067 Asar (old course), 2+6 marks
- Video: [Cache Memory ||Direct Mapping|Associative Mapping-Set Associative-Computer Organization Architecture](https://www.youtube.com/watch?v=beqOrVgxsA0) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/direct-vs-assoc-address
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-6

## Question

Why is cache management necessary in the mapping process? Differentiate between direct mapping address structure and associative mapping address structure.

## Short answer

Cache management assigns memory blocks to cache lines, checks tags for hits, handles misses, and enforces write policy. Direct mapping uses tag, line, and word fields; the line field selects one line for a single comparison. Associative mapping uses only tag and word; all tags are compared simultaneously, requiring longer tags and more hardware.

## Answer

#### Need for cache management
The cache is much smaller than main memory, so only some blocks can be stored. A mapping process is needed to decide where a block goes and how to find it again. Cache management does this job: it checks tags for a hit or miss, loads blocks on a miss, chooses a victim (replacement algorithm), keeps cache and memory consistent (write policy), and maintains valid and dirty bits. Without it the CPU could not know whether the cache holds the wanted word, nor keep the data correct.

#### Address structure
Example: 16-bit address, block of 4 words, cache of 16 lines.

| Point | Direct mapping | Associative mapping |
|---|---|---|
| Fields | Tag, Line, Word | Tag, Word |
| Example sizes | 10, 4, 2 bits | 14, 2 bits |
| Meaning of tag | Higher-order bits that identify one of the blocks sharing the line | The complete block number |
| Line field | Selects the single line to check | None, all lines are searched |
| Tag length | Shorter | Longer, so the tag memory is larger |
| Search | One comparison | Comparison with every tag |

```text
Direct:       | Tag 10b | Line 4b | Word 2b |
Associative:  | Tag 14b          | Word 2b |
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why is cache management needed?
   A. Cache holds all memory
   B. Cache is smaller, so need to decide placement, check hits and keep data correct
   C. To increase memory
   D. Remove CPU
   Answer: B. It checks tags, loads blocks, replaces, handles write policy. (Key point: Need)

2. Direct mapping address fields in example (10, 4, 2)?
   A. Tag, Line, Word
   B. Tag, Word, Line
   C. Line, Tag, Word
   D. Word, Tag, Set
   Answer: A. Tag 10b, Line 4b, Word 2b. (Key point: Direct fields)

3. Associative tag is?
   A. 10 bits, part of block
   B. 14 bits, the complete block number
   C. 4 bits
   D. 2 bits
   Answer: B. Tag 14, word 2. (Key point: Assoc tag)

4. Search in associative vs direct?
   A. Comparison with every tag vs one
   B. One vs all
   C. Both one
   D. Both none
   Answer: A. Associative compares all lines. (Key point: Search)

## Related in Computer Organization and Architecture

- [Write policy; direct vs associative mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Awp-direct-vs-assoc) — Computer Organization and Architecture, chapter 6
- [Associative cache mapping with example](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aassoc-cache-example) — Computer Organization and Architecture, chapter 6
- [Direct cache mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping) — Computer Organization and Architecture, chapter 6, asked 3×
- [Direct mapping with 32-block memory, 8-block cache](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example) — Computer Organization and Architecture, chapter 6, asked 3×
- [Cache read and direct-mapping demerits](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-demerits) — Computer Organization and Architecture, chapter 6
- [Cache mapping techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acache-mapping-techniques) — Computer Organization and Architecture, chapter 6, asked 7×

## Related in other subjects

- [Associative cache mapping](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aassociative-cache-mapping) — Embedded System, chapter 4, asked 2×
- [Cache memory mapping techniques](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-mapping-techniques) — Embedded System, chapter 4, asked 3×
- [Mapping of project management](https://www.bctengineer.com/question.md?key=semester_7%2Fict_project_management%3Apm-mapping) — ICT Project Management, chapter 6
- [Unique vs non-unique address decoding](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aunique-vs-nonunique-decoding) — Instrumentation II, chapter 2