--- title: "DMA controller block diagram and transfer" subject: "Computer Organization and Architecture" chapter: 7 key: "semester_5/computer_organization_and_architecture:dma-controller" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/dma-controller site: BCT Engineering --- # DMA controller block diagram and transfer Computer Organization and Architecture · Chapter 7: Input-Output Organization - Asked in: 2078 Kartik, 6 marks; 2078 Bhadra, 6 marks; 2076 Asoj, 8 marks; 2075 Chaitra, 5 marks; 2074 Asoj, 10 marks; 2072 Chaitra, 6 marks (asked 6 times) - Video: [Direct Memory Access ( DMA ) Controller in Computer Organization Architecture || Modes of Transfer](https://www.youtube.com/watch?v=gGB-X3KmAZU) — Sudhakar Atchala - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/dma-controller - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-7 ## Question Explain the block diagram of a DMA controller and explain how DMA is used to transfer data from a peripheral. ## Short answer A DMA controller has address and word count registers. CPU programs these, then the device raises a DMA request; the controller requests the bus, gets grant, transfers one word directly between device and memory, increments address, decrements count. When count reaches zero, it interrupts CPU. ## Answer A DMA (direct memory access) controller transfers blocks of data between an I/O device and main memory without passing each word through the CPU. #### Block diagram ```text Address bus <----> +--------------------+ (from CPU) DS --------> | Address register | RS --------> +--------------------+ RD <------> | Word count register| WR <------> +--------------------+ Data bus <------------> | Control register | +--------------------+ | Control logic | BR (bus request) <-----| | BG (bus grant) ----->| | Interrupt <-----| | DMA request <-----------| from I/O device | DMA acknowledge ----------> to I/O device | +--------------------+ ``` - **Address register:** holds the memory address of the next word to transfer; it increments after each word. - **Word count register:** holds the number of words left; it decrements after each word. When it reaches zero the transfer is finished and an interrupt is sent to the CPU. - **Control register:** sets the mode of transfer (read or write, burst or cycle stealing). - **DS, RS (DMA select, register select):** the CPU uses them with RD/WR to program the three registers through the data bus. - **BR, BG:** the DMA controller asks the CPU for the buses with BR; the CPU grants them with BG and tri-states its address, data and control lines. - **DMA request / acknowledge:** handshake lines with the I/O device. #### Data transfer from a peripheral using DMA 1. **Initialisation by CPU:** the CPU writes the starting memory address, the word count and the transfer direction into the DMA controller, and starts the device. The CPU then continues with other work. 2. **DMA request:** when the peripheral has data ready, it sends a DMA request to the controller. 3. **Bus request:** the controller sends BR to the CPU. 4. **Bus grant:** the CPU finishes its current bus cycle, floats its buses and replies with BG. 5. **Acknowledge:** the controller sends DMA acknowledge to the device and places the address register on the address bus. 6. **Transfer:** one word moves directly between the device and memory (write or read signal from the controller). The address register is incremented and the word count is decremented. 7. **Repeat or release:** in burst mode the controller keeps the bus until the block is done; in cycle-stealing mode it releases the bus after every word. 8. **Completion:** when the word count becomes zero, the controller drops BR and interrupts the CPU. The CPU then takes back control and checks the status. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What happens when the word count register reaches zero? A. Transfer starts B. Transfer finished; interrupt to CPU C. BG is sent D. Address resets only Answer: B. Zero means done, so an interrupt is sent. (Key point: Word count) 2. What are BR and BG? A. Controller requests bus; CPU grants and floats its lines B. CPU requests; controller grants C. Device requests CPU D. Interrupt lines Answer: A. BR from DMAC, BG from CPU. (Key point: BR and BG) 3. What does the CPU load initially? A. Only data B. Starting address, word count and direction C. Nothing D. Interrupt vector Answer: B. Then CPU continues other work. (Key point: Initialisation) 4. In cycle-stealing mode? A. Bus kept until block done B. Bus released after every word C. CPU halted D. No bus used Answer: B. Burst keeps the bus. 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