---
title: "DMA vs CPU memory request"
subject: "Computer Organization and Architecture"
chapter: 7
key: "semester_5/computer_organization_and_architecture:dma-vs-cpu-request"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/dma-vs-cpu-request
site: BCT Engineering
---

# DMA vs CPU memory request

Computer Organization and Architecture · Chapter 7: Input-Output Organization

- Asked in: 2076 Asoj, 2 marks
- Video: [Direct Memory Access (DMA): Working, IO Transfer Modes, and Timing Explained](https://www.youtube.com/watch?v=gTloFC8-nh8) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/dma-vs-cpu-request
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-7

## Question

How does DMA have request priority over the CPU when both request a memory transfer?

## Short answer

DMA gets higher priority because I/O devices cannot wait without data loss, while the CPU can be paused briefly. The DMA controller asserts bus request; the CPU finishes its current bus cycle, tristates its buses, and issues bus grant, allowing DMA to perform cycle stealing or burst transfers before returning control.

## Answer

The DMA controller is given higher priority on the memory bus than the CPU because an I/O device cannot wait: its data buffer would overflow or data would be lost if the transfer is delayed, whereas the CPU can simply be paused for a cycle without losing anything.

The DMA controller sends a bus request (BR) to the CPU. The CPU completes its current bus cycle, releases the address, data and control buses (high impedance), and sends bus grant (BG). The DMA controller then uses the memory for one word (cycle stealing) or a block (burst) and returns the bus to the CPU.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why is the DMA controller given higher priority than the CPU on the memory bus?
   A. An I/O device cannot wait, since its buffer would overflow and data be lost, whereas the CPU can be paused
   B. DMA is more expensive
   C. The CPU is slower than DMA
   D. DMA uses less power
   Answer: A. Delayed device data is lost, but pausing the CPU for a cycle loses nothing. (Key point: Why DMA has priority)

2. What does the CPU do before sending BG?
   A. Erases memory
   B. Disables the DMA
   C. Shuts down
   D. Completes its current bus cycle and releases address, data and control buses (high impedance)
   Answer: D. The CPU finishes the current cycle and floats the buses so the DMA can use them. (Key point: Bus grant)

3. How much does the DMA controller transfer per bus grant in cycle stealing?
   A. One word
   B. Nothing
   C. The whole block
   D. Two blocks
   Answer: A. Cycle stealing moves one word and returns the bus; burst mode moves a block. (Key point: Transfer mode)

## Related in Computer Organization and Architecture

- [DMA controller block diagram and transfer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-controller) — Computer Organization and Architecture, chapter 7, asked 6×
- [Programmed vs interrupt-driven vs DMA](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aio-techniques-compare) — Computer Organization and Architecture, chapter 7, asked 5×
- [DMA vs programmed and interrupt-driven I/O](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-overcomes) — Computer Organization and Architecture, chapter 7, asked 3×
- [I/O module functions and priority interrupt](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aio-module-priority-interrupt) — Computer Organization and Architecture, chapter 7, asked 3×
- [Isolated I/O vs memory-mapped I/O](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aisolated-vs-mmio) — Computer Organization and Architecture, chapter 7, asked 2×
- [Control memory vs main memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acontrol-vs-main-memory) — Computer Organization and Architecture, chapter 3

## Related in other subjects

- [Device controller vs kernel; DMA](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Adevice-controller-vs-kernel-dma) — Operating System, chapter 6
- [Preemptive priority and SRTF Gantt](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Apreemptive-priority-srtf-gantt) — Operating System, chapter 2
- [Why serial transfer is preferred over parallel](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-vs-parallel-preferred) — Instrumentation II, chapter 3
- [DMA controller and flow of actions](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Adma-controller-flow) — Embedded System, chapter 5, asked 3×