--- title: "Four-segment instruction pipeline and space-time diagram" subject: "Computer Organization and Architecture" chapter: 4 key: "semester_5/computer_organization_and_architecture:four-segment-pipeline" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/four-segment-pipeline site: BCT Engineering --- # Four-segment instruction pipeline and space-time diagram Computer Organization and Architecture · Chapter 4: Pipeline & Vector Processing - Asked in: 2078 Kartik, 3+5 marks; 2076 Chaitra, 10 marks; 2073 Chaitra, 10 marks; 2071 Shrawan, 6 marks; 2070 Asar, 8 marks (asked 5 times) - Video: [Instruction Pipeline | Four segment instruction pipeline | Steps of Instruction cycle](https://www.youtube.com/watch?v=yZIT5okhuXI) — Chirag Bhalodia - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/four-segment-pipeline - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-4 ## Question Explain the four segment instruction pipeline and draw its time-space diagram (e.g. for six tasks) with example. ## Short answer The four-segment pipeline (FI, DA, FO, EX) overlaps instruction processing. For 6 tasks, it takes 4+6-1 = 9 cycles instead of 24, giving a speedup of 2.67. After the pipeline fills, one instruction completes per cycle, provided no hazards stall it. ## Answer A pipeline divides a process into sub-operations (segments), and each segment works on a different task at the same time, like an assembly line. In the four-segment instruction pipeline, the instruction cycle is split into four stages, each with its own hardware and with registers between the stages, all working on the same clock. #### The four segments 1. **FI (Fetch Instruction):** read the instruction from memory. 2. **DA (Decode and calculate Address):** decode the instruction and compute the effective address. 3. **FO (Fetch Operand):** read the operand from memory. 4. **EX (Execute):** perform the operation and store the result. ```text +----+ +----+ +----+ +----+ | FI |->| DA |->| FO |->| EX | (registers between segments) +----+ +----+ +----+ +----+ ``` #### Space-time diagram for 6 tasks (instructions) T1–T6 Each column is one clock cycle (one segment time tp). ```text Segment | 1 2 3 4 5 6 7 8 9 ------------------------------------ FI | T1 T2 T3 T4 T5 T6 . . . DA | . T1 T2 T3 T4 T5 T6 . . FO | . . T1 T2 T3 T4 T5 T6 . EX | . . . T1 T2 T3 T4 T5 T6 ``` - Once the pipe is full (clock 4), one task finishes in every clock. - Number of clock cycles = k + n - 1 = 4 + 6 - 1 = **9**, where k = 4 segments and n = 6 tasks. - Without a pipeline, time = n × k = 6 × 4 = 24 cycles. - Speedup = 24 / 9 = **2.67**. For a large n, the speedup approaches k = 4. #### Example (instruction flow) For the program ADD R1,R2; SUB R3,R4; MUL R5,R6 ..., each instruction enters FI in a successive clock, so while T1 is in FO, T2 is in DA and T3 is in FI. Delays occur when a branch or a data dependency appears (the pipeline is flushed or stalled). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Order of the four segments? A. DA, FI, EX, FO B. FI, FO, DA, EX C. EX, FO, DA, FI D. FI, DA, FO, EX Answer: D. Fetch, decode, operand fetch, execute. (Key point: Segments) 2. Clock cycles for 6 tasks in 4 segments? A. 9 B. 24 C. 10 D. 6 Answer: A. k+n-1 = 4+6-1. (Key point: Clocks) 3. Speedup for 6 tasks? A. 4 B. 24/9 = 2.67 C. 6 D. 1.5 Answer: B. Non-pipelined 6x4 = 24. (Key point: Speedup) 4. Speedup approaches what for large n? A. n B. 1 C. k = 4 D. k+n Answer: C. Limit equals segments. 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