--- title: "Hardwired vs microprogrammed; sequencer diagram" subject: "Computer Organization and Architecture" chapter: 3 key: "semester_5/computer_organization_and_architecture:hardwired-vs-micro-sequencer" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/hardwired-vs-micro-sequencer site: BCT Engineering --- # Hardwired vs microprogrammed; sequencer diagram Computer Organization and Architecture · Chapter 3: Control Unit - Asked in: 2075 Chaitra, 10 marks - Video: [Hardwired Control Unit vs Microprogrammed Control Unit: Key Differences and Comparisons | COA](https://www.youtube.com/watch?v=l1vBkZWyELk) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/hardwired-vs-micro-sequencer - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-3 ## Question Differentiate between hardwired and micro-programmed control unit. Draw and explain the block diagram of the micro-programmed sequencer for control memory. ## Short answer Hardwired control uses fixed logic gates, is faster but inflexible; microprogrammed control stores microinstructions in ROM, slower but easily modified. The microprogram sequencer (next-address logic) selects the address for control memory via a multiplexer from incremented address, branch address, subroutine register, or mapped opcode, using CD and BR fields to control branching. ## Answer #### Hardwired vs microprogrammed control unit | Basis | Hardwired control unit | Microprogrammed control unit | |---|---|---| | Implementation | Fixed logic: gates, flip-flops, decoders | Microprogram stored in control memory (ROM) | | Control signals | Generated by logic circuits | Read as microinstructions | | Speed | Faster (no memory access) | Slower (one control memory access per step) | | Flexibility | Hard to change; redesign of circuit | Easy; change the microprogram | | Design | Complex, long design time, error-prone | Systematic and simpler | | Cost | Costly for complex instruction sets | Cheaper for large instruction sets | | Instruction set | Suited to RISC (small set) | Suited to CISC (large, complex set) | | Debugging | Difficult | Easy | | Use of space | Larger chip for complex logic | Needs space for control memory | | Emulation | Not possible | Possible | | Example | MIPS, many RISC chips | IBM 360, VAX, Intel x86 (partly) | #### Block diagram of the microprogram sequencer The microprogram sequencer is the part of the control unit that generates the address of the next microinstruction. It contains the next-address logic and CAR; together with the control memory, it forms the microprogrammed control unit. Mano's design has the following parts. ```text Instruction Status bits (I,S,Z) opcode (IR) | | +---v----+ +-----v-----+ | MUX 1 |<-- CD field (select) | Mapping | +---+----+ | logic | | +-----+-----+ +---v----------+ | | Input logic |<-- BR field | | (I0 I1 T) | | +---+----------+ | S1 S0 | L (load SBR) v v +--------------------------------+ AD -->| MUX 2 (selects address) |<-- SBR field | 0: CAR+1 1: branch (AD) | | 2: SBR 3: map | +---------------+----------------+ v +-----------+ +--------+ | CAR |-->| Control| +-----+-----+ | memory | | +---+----+ +-----v-----+ v | Incrementer| microinstruction +------------+ (to control data reg.) ``` #### Operation 1. The **CD field** selects one status bit (I, S, Z, or the constant 1) through MUX 1. The result is the signal T (test condition true). 2. The **BR field** (I1 I0) and T go to the **input logic**, which produces the select lines S1 S0 for MUX 2 and the load signal L for SBR: - JMP (00): S1S0 = 01 if T = 1 (branch to AD), S1S0 = 00 if T = 0 (increment). - CALL (01): same as JMP; in addition, when T = 1, L = 1 loads the return address (CAR + 1) into SBR. - RET (10): S1S0 = 10, selecting SBR. - MAP (11): S1S0 = 11, selecting the mapping logic. In Boolean form: S1 = I1, S0 = I1·I0 + I1'·T, L = I1'·I0·T. 3. **MUX 2** passes one of CAR + 1, the AD field, the SBR contents or the mapped address to CAR. 4. CAR addresses the control memory, which outputs the microinstruction into the control data register; its fields drive the datapath. 5. The incrementer forms CAR + 1, which is input 0 of MUX 2 and is the value stored in SBR during a CALL. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which control unit is faster? A. Microprogrammed B. Equal C. Hardwired D. Depends on ROM only Answer: C. No memory access per step. (Key point: Speed) 2. Which is easier to debug and modify? A. Hardwired B. Equal C. Neither D. Microprogrammed Answer: D. Change microcode. (Key point: Debugging) 3. For JMP with T = 1, what does the input logic select? A. S = 10 (branch AD) B. S = 00 C. S = 11 D. S = 01 Answer: A. T=0 gives 00 (CAR+1). (Key point: JMP select) 4. What extra does CALL do? A. Selects mapping B. L = 1 saves the return address in SBR C. Clears CAR D. Stops the clock Answer: B. CAR+1 from the incrementer is stored. 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