--- title: "Instruction cycle state diagram with interrupt" subject: "Computer Organization and Architecture" chapter: 1 key: "semester_5/computer_organization_and_architecture:instr-cycle" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/instr-cycle site: BCT Engineering --- # Instruction cycle state diagram with interrupt Computer Organization and Architecture · Chapter 1: Introduction - Asked in: 2079 Baisakh, 4 marks; 2076 Chaitra, 6 marks; 2074 Chaitra, 6 marks; 2074 Asoj, 6 marks; 2073 Chaitra, 6 marks; 2071 Shrawan, 3 marks (asked 6 times) - Video: [Instruction Cycle State Transition Diagram in Computer Organization & Architecture | COA](https://www.youtube.com/watch?v=qfbG-TA6st4) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/instr-cycle - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-1 ## Question Explain the instruction cycle state diagram with interrupt. ## Short answer The instruction cycle comprises states: iac, if, iod, oac, of, do, os. After os, an interrupt check occurs; if a signal is pending and interrupts enabled, the CPU saves state, jumps to the service routine, and later resumes the program. ## Answer The instruction cycle is the sequence of steps the CPU repeats to execute one instruction: fetch the instruction, decode it, fetch operands, execute, store the result, and then check for interrupts. The state diagram shows these steps as states with arrows for the transitions. ```text iac --> if --> iod --> oac --> of --> do --> oac --> os ^ ^ | ^ | | +------+ +-------+ | more operands more results | | +-- no interrupt <-- interrupt check <---------------+ | interrupt --> interrupt processing ``` #### States of the diagram 1. **Instruction address calculation (iac):** find the address of the next instruction (usually PC + length). 2. **Instruction fetch (if):** read the instruction from memory into IR. 3. **Instruction operation decoding (iod):** find the operation type and the operands needed. 4. **Operand address calculation (oac):** if an operand is in memory (indirect or indexed), calculate its address. 5. **Operand fetch (of):** read the operand from memory or I/O. This pair (oac, of) repeats if there are several operands. 6. **Data operation (do):** the ALU performs the operation. 7. **Operand store (os):** write the result to memory, register or I/O. Multiple results repeat this step. #### Interrupt handling After each instruction the CPU checks for an interrupt signal. If none is pending, it goes to the next instruction. If one is pending and interrupts are enabled, the CPU: - saves the current PC and processor status (usually on the stack), - loads the PC with the address of the interrupt service routine, - runs the routine, then restores the saved state and resumes the interrupted program. The interrupt check is placed at the end of the cycle so that an instruction is never cut in half. The fetch and execute parts can also be shown as two main phases: the **fetch cycle** (iac, if) and the **execute cycle** (iod to os), with the **interrupt cycle** added when needed. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Where is the interrupt check placed in the instruction cycle, and why? A. At the end of the cycle, so an instruction is never cut in half B. At the start of instruction fetch, so interrupts are served first C. In the middle of the execute step, to reduce latency D. After every state, so the CPU responds at once Answer: A. The CPU checks for interrupts after each instruction finishes, so no instruction is interrupted part-way. (Key point: Interrupt check position) 2. What happens when an instruction has several operands? A. The whole cycle restarts from iac B. Only the first operand is fetched; the rest are implied C. The oac and of states repeat for each operand D. The iod state repeats for each operand Answer: C. The pair operand address calculation and operand fetch loops until all operands are read. (Key point: Operand address calculation and fetch) 3. If an interrupt is pending and enabled, what does the CPU do? A. Saves PC and status, loads PC with the ISR address, runs the ISR, then restores state B. Discards the current program and starts the ISR C. Loads PC with the ISR address without saving anything D. Finishes the whole program, then runs the ISR Answer: A. The CPU must save the PC and status so the interrupted program can resume after the service routine. (Key point: Interrupt processing steps) 4. Which state comes immediately after instruction fetch (if) in the diagram? A. Operand fetch (of) B. Data operation (do) C. Instruction operation decoding (iod) D. Instruction address calculation (iac) Answer: C. After the instruction is read into IR, it is decoded to find the operation and operands needed. (Key point: State order) ## Related in Computer Organization and Architecture - [Four-segment instruction pipeline and space-time diagram](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Afour-segment-pipeline) — Computer Organization and Architecture, chapter 4, asked 5× ## Related in other subjects - [Instruction cycle and machine cycle](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainstruction-cycle-machine-cycle) — Microprocessor, chapter 1, asked 2× - [RIM instruction in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-rim) — Microprocessor, chapter 5 - [Interfacing 8-bit ADC using interrupt](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-interrupt-interface) — Instrumentation II, chapter 4, asked 2× - [Machine cycle, T-states, ANI 55H timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amachine-cycle-tstate-ani-55h) — Microprocessor, chapter 2