---
title: "Instruction format and its types"
subject: "Computer Organization and Architecture"
chapter: 2
key: "semester_5/computer_organization_and_architecture:instr-format"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/instr-format
site: BCT Engineering
---

# Instruction format and its types

Computer Organization and Architecture · Chapter 2: Central Processing Unit

- Asked in: 2072 Chaitra, 4 marks; 2071 Shrawan, 2 marks; 2069 Chaitra, 10 marks (asked 3 times)
- Video: [L-1.13: What is Instruction Format | Understand Computer Organisation with Simple Story](https://www.youtube.com/watch?v=WAO_W6Hpzyk) — Gate Smashers
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/instr-format
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-2

## Question

What do you mean by instruction format? Explain the different types of instruction formats with example.

## Short answer

Instruction format is the bit layout with opcode, mode, and address fields. Formats are classified by operand count: three-address (short code, long instruction), two-address (common, e.g. ADD R1,B), one-address (uses accumulator), and zero-address (stack-based, only PUSH/POP have addresses).

## Answer

An instruction format is the layout of the bits of an instruction, divided into fields. It defines the opcode, the operand addresses and the addressing mode. The size and fields of the instruction depend on the CPU organization.

#### Fields
- **Opcode:** the operation to perform.
- **Mode:** how to find the operand.
- **Address field(s):** operand or register address (or the operand itself).

#### Types by number of addresses
**1. Three-address format:** `OPCODE | DEST | SRC1 | SRC2`. Example: ADD R1, A, B means R1 = M[A] + M[B]. Short programs, long instructions.

**2. Two-address format:** `OPCODE | DEST/SRC1 | SRC2`. Example: ADD R1, B means R1 = R1 + M[B]. The destination is also a source. Most common in commercial machines.

**3. One-address format:** `OPCODE | ADDRESS`. The accumulator is the second, implied operand. Example: ADD B means AC = AC + M[B].

**4. Zero-address format:** `OPCODE` only. Operands are on the top of a stack. Example: ADD pops two items, adds and pushes the result. PUSH A / POP A need one address.

For X = (A+B)*(C+D):
```text
3-addr: ADD R1,A,B   ADD R2,C,D   MUL X,R1,R2
2-addr: MOV R1,A  ADD R1,B  MOV R2,C  ADD R2,D  MUL R1,R2  MOV X,R1
1-addr: LOAD A  ADD B  STORE T  LOAD C  ADD D  MUL T  STORE X
0-addr: PUSH A PUSH B ADD PUSH C PUSH D ADD MUL POP X
```

#### By length
- **Fixed length** (RISC): simple decoding, easy pipelining.
- **Variable length** (CISC): saves memory but needs more complex decoding.

#### Other types
- **Register-reference, memory-reference, I/O** formats in the basic computer, separated by mode and opcode bits.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. An instruction format is
   A. The number of instructions
   B. The layout of the bits of an instruction in fields
   C. The clock speed
   D. The memory map
   Answer: B. It defines opcode, operand addresses and mode. (Key point: Definition)

2. In a zero-address format, operands are
   A. In the accumulator
   B. In registers named in the instruction
   C. In memory addresses
   D. On top of a stack
   Answer: D. Stack machines use PUSH and POP. (Key point: Zero-address)

3. In a one-address instruction ADD B, the other operand is
   A. The stack
   B. The accumulator
   C. A register named
   D. The PC
   Answer: B. AC = AC + M[B]. (Key point: One-address)

4. Fixed-length instructions are used in
   A. CISC to save memory
   B. Never
   C. Only zero-address
   D. RISC, for simple decoding
   Answer: D. They ease pipelining. (Key point: Fixed length)

## Related in Computer Organization and Architecture

- [Instruction fields and address formats for X=(E+F)*(G+H)](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acode-fields-e-f-g-h) — Computer Organization and Architecture, chapter 2
- [Address-format code for Y=(A+B)*(C+D)](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-code-7) — Computer Organization and Architecture, chapter 2, asked 16×
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- [Address-format code for X=(P+Q)×(R+S)](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-code-2) — Computer Organization and Architecture, chapter 2, asked 16×
- [Address-format code for Y=A*(B+D/C)+(G*E)/F](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-code-3) — Computer Organization and Architecture, chapter 2, asked 16×
- [Address-format code for Y=A/(B+C)+(D+E)*F](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-code-4) — Computer Organization and Architecture, chapter 2, asked 16×

## Related in other subjects

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