--- title: "Interconnection structure of computer" subject: "Computer Organization and Architecture" chapter: 1 key: "semester_5/computer_organization_and_architecture:interconnection-structure" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/interconnection-structure site: BCT Engineering --- # Interconnection structure of computer Computer Organization and Architecture · Chapter 1: Introduction - Asked in: 2075 Asoj, 6 marks; 2073 Shrawan, 2+4 marks; 2070 Chaitra, 3+3 marks (asked 3 times) - Video: [Interconnection structures in computer architecture #engineering](https://www.youtube.com/watch?v=7UmYfl9SqfQ) — MADE_EASY_FOR_YOU - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/interconnection-structure - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-1 ## Question What do you mean by interconnection structure? Explain the interconnection of CPU with memory and I/O devices and the different types of interconnections and operations over them. ## Short answer The interconnection structure links CPU, memory, and I/O modules. Transfers include memory read/write, I/O read/write, and DMA. Common interconnection types are shared bus, bus hierarchy, and point-to-point. A bus operation involves arbitration, then placing address, control, and data. ## Answer The interconnection structure is the collection of paths that connect the main modules of a computer (CPU, memory and I/O modules) so that they can exchange data and control information. Its design depends on what each module needs to send and receive. #### Modules and their transfers ```text +-----+ data / address / control +--------+ | CPU |<==========================>| Memory | +-----+ +--------+ ^ ^ | +------------+ | +------->| I/O module |<------------+ +------------+ (DMA) | | Peripheral devices ``` - **Memory module:** has N words with unique addresses. It accepts Read and Write control signals, an address and data. - **I/O module:** seen from inside the computer, it works like memory (read and write), but it also controls one or more external devices and can send **interrupt** signals to the CPU. - **CPU:** reads instructions and data, writes data, sends control signals, and receives interrupts. #### Types of transfers (operations) 1. Memory to CPU: the CPU reads an instruction or data. 2. CPU to memory: the CPU writes data. 3. I/O to CPU: the CPU reads data from an I/O device through an I/O module. 4. CPU to I/O: the CPU sends data to an I/O device. 5. I/O to or from memory: direct memory access (DMA), without the CPU. #### Types of interconnections - **Bus structure:** a shared communication path made of address, data and control lines. Only one device can send at a time. This is the most common structure. - **Multiple buses (bus hierarchy):** a local bus, a system bus and an expansion bus, joined by bridges, to reduce the load on each bus. - **Point-to-point (crossbar or switch):** each pair of modules has its own direct link. This is used in modern processors (for example QuickPath, HyperTransport, PCI Express). #### Operation on a bus To send data, a module must (1) obtain the use of the bus (arbitration), then (2) place the address, control signals and data on the lines. For a read, the CPU sends the address and a Read signal, and the memory places the data on the data bus. For a write, the CPU sends the address, the data and a Write signal, and the memory stores the data. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the interconnection structure? A. The set of instructions the CPU supports B. The internal wiring of the ALU only C. The software layer between OS and hardware D. The collection of paths connecting CPU, memory and I/O modules Answer: D. It is the set of paths used to exchange data and control information between the main modules. (Key point: Definition) 2. Which transfer takes place without the CPU? A. Memory to CPU B. I/O to or from memory by DMA C. CPU to memory D. CPU to I/O Answer: B. Direct memory access moves data between I/O and memory without passing through the CPU. (Key point: DMA transfer) 3. Which is a point-to-point interconnection used in modern processors? A. A single shared system bus B. Daisy chain C. Multiplexed address bus D. PCI Express Answer: D. Point-to-point links such as QuickPath, HyperTransport and PCI Express give each pair its own link. (Key point: Types of interconnections) 4. In a bus read from memory, what happens? A. The CPU places data on the bus and the memory stores it B. The CPU sends address and Read signal and the memory places data on the data bus C. The memory sends the address to the CPU D. The I/O module sends the data first Answer: B. For a read the CPU supplies address and Read, and memory responds with the data after bus arbitration. (Key point: Bus read operation) ## Related in Computer Organization and Architecture - [DMA vs CPU memory request](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-vs-cpu-request) — Computer Organization and Architecture, chapter 7 - [Functional view and operations of a computer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Afunctional-view) — Computer Organization and Architecture, chapter 1 - [Bus structure of a typical computer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Abus-structure) — Computer Organization and Architecture, chapter 1 - [Bus interconnection](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Abus-interconnection) — Computer Organization and Architecture, chapter 1, asked 2× - [CPU and IOP communication](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acpu-iop-communication) — Computer Organization and Architecture, chapter 7, asked 2× - [General register organization in CPU](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acpu-register-org) — Computer Organization and Architecture, chapter 2 ## Related in other subjects - [Memory devices; PAL vs PLA](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apal-vs-pla) — Digital Logic, chapter 4 - [Data structure types and operations](https://www.bctengineer.com/question.md?key=semester_4%2Fdata_structure_and_algorithm%3Adata-structure-types-operations) — Data Structure and Algorithm, chapter 1 - [Data structure and basic operations](https://www.bctengineer.com/question.md?key=semester_4%2Fdata_structure_and_algorithm%3Adata-structure-basic-operations) — Data Structure and Algorithm, chapter 1 - [CPU simulation with example](https://www.bctengineer.com/question.md?key=semester_8%2Fsimulation_and_modeling%3Acpu-simulation-example) — Simulation and Modeling, chapter 10, asked 4×