--- title: "I/O module functions and priority interrupt" subject: "Computer Organization and Architecture" chapter: 7 key: "semester_5/computer_organization_and_architecture:io-module-priority-interrupt" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/io-module-priority-interrupt site: BCT Engineering --- # I/O module functions and priority interrupt Computer Organization and Architecture · Chapter 7: Input-Output Organization - Asked in: 2079 Baisakh, 10 marks; 2071 Shrawan, 3+7 marks; 2069 Chaitra, 10 marks (asked 3 times) - Video: [I/O Interface in Computer Organization](https://www.youtube.com/watch?v=PM728r4oGcE) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/io-module-priority-interrupt - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-7 ## Question What are the functions of an I/O module? Why is priority interrupt needed for data transmission between CPU and I/O device? Explain the types of priority interrupt in detail. ## Short answer Functions of I/O module: control/timing, processor/device communication, data buffering, error detection, address decoding. Priority interrupt is needed to order simultaneous requests by urgency and allow higher-priority preemption. Types: software polling (slow, tests devices in order), daisy chain (serial priority, hardware chain), and parallel priority (uses interrupt register and encoder for fast, maskable selection). ## Answer #### Functions of an I/O module 1. **Control and timing:** coordinates the flow of data between the CPU, memory and device. 2. **Processor communication:** decodes commands, exchanges data and reports status to the CPU. 3. **Device communication:** sends commands to the device and reads its status. 4. **Data buffering:** holds data to match the slow device speed with the fast CPU. 5. **Error detection:** detects device or transmission errors (for example parity) and reports them. 6. **Address decoding and conversion:** identifies the addressed device and converts data format. #### Need for priority interrupt Many devices may request service at the same time, or a new request may arrive while another is being served. The system needs a rule to decide which one is served first. A priority interrupt system establishes this order: urgent and fast devices (for example a disk) are given a higher priority than slow ones (for example a keyboard), it identifies the interrupting device, and a higher-priority interrupt can interrupt a lower-priority service routine. It also allows masking of chosen interrupts. #### Types of priority interrupt 1. **Software polling (polling):** on any interrupt, a single branch address starts a polling routine that tests each device's status flag in priority order. The first device found with its flag set is serviced. It is simple and needs little hardware, but it is slow because identifying the device takes a long time. 2. **Daisy chaining (serial priority):** all devices share one interrupt request line. The interrupt acknowledge signal passes through the devices in series, starting from the highest priority one. The first requesting device blocks the signal and puts its vector address on the data bus. Cheap, but a failure breaks the chain and low-priority devices may starve. 3. **Parallel priority:** each device has its own bit in an **interrupt register** and a bit in a **mask register**. A priority encoder gives the highest-priority unmasked request, generating a vector address. Fast and flexible (masking) but needs more hardware. ```text Daisy chain: CPU INTACK -> [Dev1 PI/PO] -> [Dev2] -> [Dev3] -> ... Interrupt request line (common, wired OR) <- all devices Parallel priority: Dev0..Dev3 -> Interrupt reg & Mask reg -> Priority encoder -> vector (x y) -> CPU ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why does an I/O module provide data buffering? A. To store the operating system B. To increase the clock speed of the CPU C. To encrypt data sent to the device D. To match the slow device speed with the fast CPU Answer: D. A buffer holds data so the fast CPU and the slow device can each work at their own speed. (Key point: Data buffering) 2. Why is a priority interrupt system needed? A. Because it removes the need for interrupt service routines B. Because the CPU cannot execute interrupts without it C. Because it makes every device run at the same speed D. Because several devices may request service at once and the system needs a rule to decide which is served first Answer: D. Simultaneous or nested requests need an order of service; priority interrupt provides that order, and lets urgent devices like a disk win over a keyboard. (Key point: Need for priority interrupt) 3. In daisy chaining, what does the first requesting device in the chain do with the interrupt acknowledge signal? A. Blocks it and puts its vector address on the data bus B. Ignores it and raises a second request C. Passes it on to the next device D. Sends it back to the CPU as an error Answer: A. The first device with a pending request blocks the acknowledge signal and supplies its vector address, so lower-priority devices behind it do not get it. (Key point: Daisy chaining) 4. Which hardware is used in parallel priority interrupt? A. A DMA controller with a word count register B. A single status flag tested by software in a loop C. A serial chain of PI/PO lines only D. An interrupt register, a mask register and a priority encoder Answer: D. Each device has a bit in the interrupt and mask registers, and a priority encoder picks the highest-priority unmasked request and gives the vector. (Key point: Parallel priority) ## Related in Computer Organization and Architecture - [Types of priority interrupt](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Apriority-interrupt) — Computer Organization and Architecture, chapter 7 - [DMA vs CPU memory request](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-vs-cpu-request) — Computer Organization and Architecture, chapter 7 - [Identifying the interrupting device](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ainterrupt-device-id) — Computer Organization and Architecture, chapter 7 ## Related in other subjects - [Interrupt driven data transfer](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ainterrupt-driven-transfer) — Instrumentation II, chapter 1, asked 2× - [Error detection in serial data transmission](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-error-detection) — Instrumentation II, chapter 3, asked 2× - [Types of data transmission technology](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Adata-transmission-technologies) — Data Communication, chapter 1 - [Functions of data link layer](https://www.bctengineer.com/question.md?key=semester_7%2Fcomputer_networks_and_security%3Adll-functions) — Computer Networks and Security, chapter 3, asked 3×