---
title: "Interprocessor synchronization"
subject: "Computer Organization and Architecture"
chapter: 8
key: "semester_5/computer_organization_and_architecture:ipc-sync"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/ipc-sync
site: BCT Engineering
---

# Interprocessor synchronization

Computer Organization and Architecture · Chapter 8: Multiprocessors

- Asked in: 2075 Chaitra, 4 marks; 2072 Chaitra, 4 marks; 2070 Asar, 4 marks (asked 3 times)
- Video: [Inter Processor Communication and Synchronization in Computer Organization Architecture](https://www.youtube.com/watch?v=2z2DctUtHTQ) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/ipc-sync
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-8

## Question

Explain interprocessor synchronization with a suitable mechanism and example.

## Short answer

Interprocessor synchronization is achieved via mutual exclusion using a binary semaphore and an atomic test-and-set (TSL) instruction. A processor reads and sets the lock in one indivisible operation; if busy, it loops. For example, two processors updating a shared counter use TSL to ensure only one enters the critical section at a time.

## Answer

Interprocessor synchronization is the coordination of processors that share data or resources, to make sure that the order of operations is right. **Mutual exclusion** is needed so that only one processor uses a shared resource (a critical section) at a time. It is implemented with a **binary semaphore** (a variable in shared memory: 0 = free, 1 = in use).

#### Mechanism: test-and-set (TSL) instruction
The processor reads the semaphore and sets it to 1 in one indivisible (atomic) memory cycle, locking out other processors from the memory during it:

```text
TSL SEM:   R <- M[SEM] ;  M[SEM] <- 1      (atomic)

Entry:     TSL SEM          ; test and set
           CMP R, #0        ; was it free?
           BNE Entry        ; no, loop (busy wait)
           ... critical section ...
Exit:      CLR SEM          ; M[SEM] <- 0 releases the lock
```

#### Example
Processors P1 and P2 both want to update a shared counter. P1 executes TSL: R = 0, the semaphore becomes 1, so P1 enters the critical section. P2 executes TSL: R = 1, so it keeps looping. When P1 finishes, it clears the semaphore to 0. P2's next TSL gets R = 0 and then P2 enters. This prevents both from updating the counter at the same time.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does mutual exclusion ensure?
   A. Memory is erased
   B. Processors run at equal speed
   C. Only one processor uses a shared resource (critical section) at a time
   D. All processors run the same code
   Answer: C. It prevents simultaneous updates of a shared resource. (Key point: Mutual exclusion)

2. In the answer, what does a binary semaphore value of 1 mean?
   A. The processor is off
   B. The resource is free
   C. The resource is in use
   D. An error
   Answer: C. 0 = free, 1 = in use. (Key point: Binary semaphore)

3. Why must test-and-set be indivisible?
   A. To make it faster
   B. To save memory
   C. To reset the semaphore
   D. So two processors cannot both read 0 and enter the critical section
   Answer: D. Atomic read-and-set locks out other processors during the operation. (Key point: Atomic TSL)

4. In the example, what does P2 get from TSL while P1 is inside the critical section?
   A. An interrupt
   B. R = 0 and it enters
   C. R = 1 and it keeps looping
   D. A memory error
   Answer: C. The semaphore is 1, so P2 busy-waits until P1 clears it. (Key point: Example)