---
title: "Memory characteristics and LRU replacement"
subject: "Computer Organization and Architecture"
chapter: 6
key: "semester_5/computer_organization_and_architecture:memory-char-lru"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/memory-char-lru
site: BCT Engineering
---

# Memory characteristics and LRU replacement

Computer Organization and Architecture · Chapter 6: Memory System

- Asked in: 2073 Chaitra, 8 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/memory-char-lru
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-6

## Question

Explain the major characteristics of memory. Explain the LRU (Least Recently Used) replacement policy with example.

## Short answer

Memory characteristics: location, capacity, unit of transfer, access method, performance, physical type, volatility, and organization. LRU replacement evicts the block unused for the longest time by tracking usage order. In a 4-block cache with accesses 2,3,2,1,5,2,4,5,3,2,5,2, hits=6, misses=6, hit ratio=0.5.

## Answer

#### Characteristics of memory

| Characteristic | Meaning | Examples |
|---|---|---|
| **Location** | Where the memory is: internal (registers, cache, main memory), external (disk, tape) | CPU registers, RAM, HDD |
| **Capacity** | Size: words or bytes for internal, bytes for external | 8 GB RAM, 1 TB disk |
| **Unit of transfer** | Data moved in one access: word for internal, block for external | Word, block, record |
| **Access method** | Sequential (tape), direct (disk), random (RAM), associative (cache tag search) | Tape, disk, RAM, cache |
| **Performance** | Access time (latency), memory cycle time, transfer rate = 1 / cycle time | DRAM access: tens of ns |
| **Physical type** | Semiconductor, magnetic, optical, magneto-optical | RAM, HDD, CD |
| **Physical characteristics** | Volatile or non-volatile; erasable or non-erasable | RAM volatile, ROM non-volatile |
| **Organisation** | Physical arrangement of bits into words | Interleaved memory banks |

#### LRU replacement policy

**LRU (Least Recently Used)** replaces the cache block that has not been used for the longest time. It uses temporal locality: a block used recently is likely to be used again soon. The hardware keeps an age (or use) counter for each line; on each access the age of the used line is reset and others are increased.

- **Hit:** the block is in the cache; no replacement. The block becomes the most recently used.
- **Miss with free line:** the block is loaded into a free line and becomes the most recently used.
- **Miss with cache full:** the least recently used block is removed and the new block is loaded.

#### Example: cache of 4 blocks, reference string 2, 3, 2, 1, 5, 2, 4, 5, 3, 2, 5, 2
```text
Ref  Result            Cache (most recent first)
2    Miss              [2]
3    Miss              [3, 2]
2    Hit               [2, 3]
1    Miss              [1, 2, 3]
5    Miss              [5, 1, 2, 3]
2    Hit               [2, 5, 1, 3]
4    Miss (evict 3)    [4, 2, 5, 1]
5    Hit               [5, 4, 2, 1]
3    Miss (evict 1)    [3, 5, 4, 2]
2    Hit               [2, 3, 5, 4]
5    Hit               [5, 2, 3, 4]
2    Hit               [2, 5, 3, 4]
```

Hits = 6, misses = 6, hit ratio = 6/12 = 0.50. When 4 was referenced the cache was full and the least recently used block was 3, so 3 was evicted; when 3 came back, block 1 was the least recently used, so 1 was evicted.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which pairing of memory and access method is correct?
   A. Tape - random
   B. RAM - sequential
   C. Disk - direct
   D. Cache - sequential
   Answer: C. Tape is sequential, disk direct, RAM random and cache tag search associative. (Key point: Access methods)

2. How is transfer rate related to memory cycle time?
   A. Transfer rate = cycle time
   B. Transfer rate = 1 / cycle time
   C. Transfer rate = cycle time^2
   D. They are unrelated
   Answer: B. One word can be transferred per cycle, so rate is the reciprocal of cycle time. (Key point: Performance)

3. Which block does LRU replace when the cache is full?
   A. The block loaded first
   B. The block used fewest times
   C. The block unused for the longest time
   D. A random block
   Answer: C. LRU uses temporal locality and removes the least recently used block. (Key point: LRU principle)

4. In the 4-block example, which block is evicted when 4 is referenced and why?
   A. Block 1, loaded earliest
   B. Block 3, least recently used
   C. Block 5, used most
   D. Block 2, used most recently
   Answer: B. Before 4 the order is [2,5,1,3] most recent first, so 3 is least recently used. (Key point: LRU example)

5. The example string has 6 hits in 12 references. What is the hit ratio?
   A. 0.25
   B. 0.33
   C. 0.50
   D. 0.75
   Answer: C. 6/12 = 0.50. (Key point: LRU hit ratio)

## Related in Computer Organization and Architecture

- [LRU replacement with hit and miss](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Alru-replacement) — Computer Organization and Architecture, chapter 6
- [Direct mapping with 32-block memory, 10 blocks used](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example-10) — Computer Organization and Architecture, chapter 6, asked 3×
- [Direct mapping with 64-block memory, 10 blocks used](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example-64) — Computer Organization and Architecture, chapter 6, asked 3×
- [Characteristics of memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amemory-characteristics) — Computer Organization and Architecture, chapter 6, asked 4×
- [Cache write policy techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Awrite-policy) — Computer Organization and Architecture, chapter 6
- [Mapping function and replacement algorithm](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amapping-replacement) — Computer Organization and Architecture, chapter 6

## Related in other subjects

- [Cache write policy and replacement algorithm](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-write-policy-replacement) — Embedded System, chapter 4
- [Major characteristics of Bluetooth](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Abt-characteristics) — Instrumentation II, chapter 5
- [Page faults: FIFO, Optimal, LFU, LRU](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Apage-faults-fifo-optimal-lfu-lru-5frames) — Operating System, chapter 4, asked 2×
- [Page faults with 3 frames: LRU, FIFO, OPT](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Apage-fault-circumstances-lru-fifo-optimal) — Operating System, chapter 4, asked 2×
