---
title: "Microinstruction fields and sequencing techniques"
subject: "Computer Organization and Architecture"
chapter: 3
key: "semester_5/computer_organization_and_architecture:microinstr-fields-seq"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microinstr-fields-seq
site: BCT Engineering
---

# Microinstruction fields and sequencing techniques

Computer Organization and Architecture · Chapter 3: Control Unit

- Asked in: 2074 Asoj, 10 marks
- Video: [Address Sequencing || Microprogram Sequencer || Computer Organization Architecture](https://www.youtube.com/watch?v=nxNytEYQLKI) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microinstr-fields-seq
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-3

## Question

Describe the various fields in a microinstruction format. Explain the sequencing techniques used in microinstruction format with necessary diagrams.

## Short answer

A microinstruction has F1-F3 for microoperations, CD for condition, BR for branch type, and AD for address. Sequencing increments CAR, uses conditional/unconditional branch to AD, maps opcode to routine address, and supports subroutine CALL/RET via the SBR.

## Answer

#### Fields of a microinstruction
A microinstruction (20 bits in Mano's design) has:
- **F1, F2, F3 (3 bits each):** microoperation fields. Each selects a microoperation to execute at the same time as the other two (for example F1 = 110 PCTAR, F2 = 100 READ, F3 = 101 INCPC).
- **CD (2 bits):** condition field. 00 = U (unconditional), 01 = I (indirect bit), 10 = S (sign bit of AC), 11 = Z (AC zero).
- **BR (2 bits):** branch field: 00 JMP, 01 CALL, 10 RET, 11 MAP.
- **AD (7 bits):** address field, giving the branch address.

```text
 | F1(3) | F2(3) | F3(3) | CD(2) | BR(2) | AD(7) |
```

#### Sequencing techniques
Sequencing means selecting the address of the next microinstruction. The techniques are:

1. **Incrementing CAR:** the microinstructions of a routine are stored in sequence, so CAR ← CAR + 1 is the default.
2. **Unconditional branching:** BR = JMP with CD = U, so CAR ← AD.
3. **Conditional branching:** CD selects a status bit; if it is 1, CAR ← AD, otherwise CAR ← CAR + 1.
4. **Mapping:** at the end of fetch, the opcode is mapped to the routine address (0 + opcode + 00).
5. **Subroutine call and return:** CALL saves CAR + 1 in the subroutine register SBR and jumps to AD; RET loads CAR ← SBR. A common routine (like INDRCT) can be shared by many routines.

```text
   opcode --> mapping ------+
   AD field ----------------+--> [ MUX ] --> CAR --> Control mem
   SBR ----------------------+      ^
   CAR + 1 -------------------------+
                          select by  CD, BR, status
```
Sequencing lets the control unit branch on status bits and reuse common routines, which keeps the microprogram short.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How does a conditional branch work?
   A. CAR<-AD always
   B. CAR<-SBR if true
   C. CAR is cleared if false
   D. If the selected status bit is 1, CAR<-AD; otherwise CAR<-CAR+1
   Answer: D. CD picks the bit. (Key point: Conditional branch)

2. What is the default next address?
   A. CAR + 1
   B. AD
   C. SBR
   D. The mapped address
   Answer: A. Routines are stored in sequence. (Key point: Default sequencing)

3. When is mapping used and what address does it give?
   A. At start of indirect; 1 + opcode
   B. At end of fetch; 0 + opcode + 00
   C. After every JMP; AD + 1
   D. On reset; 64
   Answer: B. Gives routine start address for the opcode. (Key point: Mapping)

4. Why use CALL and RET?
   A. To speed up the ALU
   B. To avoid using CAR
   C. A common routine like INDRCT is shared by many routines, keeping the microprogram short
   D. To map the opcode
   Answer: C. CALL saves CAR+1 in SBR; RET restores it. (Key point: Subroutine)

## Related in Computer Organization and Architecture

- [Microinstruction format and microprogram design](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-fetch-indirect-add) — Computer Organization and Architecture, chapter 3
- [Microinstruction format](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroinstr-format) — Computer Organization and Architecture, chapter 3, asked 4×
- [Microinstruction format and fetch microprogram](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroinstr-format-fetch) — Computer Organization and Architecture, chapter 3, asked 2×
- [Instruction fields and address formats for X=(E+F)*(G+H)](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acode-fields-e-f-g-h) — Computer Organization and Architecture, chapter 2

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