--- title: "Microinstruction format and fetch microprogram" subject: "Computer Organization and Architecture" chapter: 3 key: "semester_5/computer_organization_and_architecture:microinstr-format-fetch" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microinstr-format-fetch site: BCT Engineering --- # Microinstruction format and fetch microprogram Computer Organization and Architecture · Chapter 3: Control Unit - Asked in: 2074 Asoj, 10 marks; 2073 Shrawan, 6+4 marks (asked 2 times) - Video: [Understanding Microinstruction Format for Control Memory || Lesson 41 || Computer Organization ||](https://www.youtube.com/watch?v=dhxdTMRp81c) — Wisdomers - Computer Science and Engineering - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microinstr-format-fetch - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-3 ## Question Explain the microinstruction format used in a microprogrammed control unit and write the micro program for the fetch cycle. ## Short answer The format uses three 3-bit fields (F1, F2, F3) for microoperations, a 2-bit CD condition, a 2-bit BR branch type, and a 7-bit AD. The fetch routine at address 64 does: PCTAR; then READ,INCPC; then DRTAR with MAP to branch to the execute routine of the fetched instruction. ## Answer A microprogrammed control unit stores in its control memory a microprogram for each instruction. Each microinstruction has fields which select microoperations and the address of the next microinstruction. #### Microinstruction format (Mano, 20 bits) ```text | F1 | F2 | F3 | CD | BR | AD | | 3 | 3 | 3 | 2 | 2 | 7 | = 20 bits ``` | Field | Bits | Meaning | |---|---|---| | F1, F2, F3 | 3 each | Three microoperation fields. Each selects one of 7 microoperations (000 = none), so up to 3 can be done at the same time. | | CD | 2 | Condition: 00 = U (always 1), 01 = I (indirect bit DR(15)), 10 = S (sign of AC), 11 = Z (AC is zero) | | BR | 2 | Branch type: 00 JMP, 01 CALL, 10 RET, 11 MAP | | AD | 7 | Address of the next microinstruction when branching (control memory of 128 words) | Microoperation codes: | F1 | Operation | F2 | Operation | F3 | Operation | |---|---|---|---|---|---| | 001 | AC ← AC + DR | 001 | AC ← AC - DR | 001 | AC ← AC xor DR | | 010 | AC ← 0 | 010 | AC ← AC or DR | 010 | AC ← AC' | | 011 | AC ← AC + 1 | 011 | AC ← AC and DR | 011 | shl AC | | 100 | AC ← DR | 100 | DR ← M[AR] | 100 | shr AC | | 101 | AR ← DR(0-10) | 101 | DR ← AC | 101 | PC ← PC + 1 | | 110 | AR ← PC | 110 | DR ← DR + 1 | 110 | PC ← AR | | 111 | M[AR] ← DR | 111 | DR(0-10) ← PC | 111 | not used | The fields can be written symbolically, for example `READ, INCPC U JMP NEXT`, which uses F2 and F3 with an unconditional jump to the next address. #### Fetch cycle microprogram The fetch cycle needs these register transfers: AR ← PC; DR ← M[AR], PC ← PC + 1; AR ← DR(0–10), then branch to the routine of the opcode (MAP). The fetch routine starts at address 64 of the control memory. | Address (dec / bin) | Label | Microoperations | CD | BR | AD | Binary F1 F2 F3 CD BR AD | |---|---|---|---|---|---|---| | 64 / 1000000 | FETCH | PCTAR | U | JMP | NEXT | 110 000 000 00 00 1000001 | | 65 / 1000001 | - | READ,INCPC | U | JMP | NEXT | 000 100 101 00 00 1000010 | | 66 / 1000010 | - | DRTAR | U | MAP | 0 | 101 000 000 00 11 0000000 | Symbolic form: ```text ORG 64 FETCH: PCTAR U JMP NEXT ; AR <- PC READ, INCPC U JMP NEXT ; DR <- M[AR], PC <- PC + 1 DRTAR U MAP ; AR <- DR(0-10), go to routine ``` The MAP microinstruction takes the opcode from DR and maps it to the start address of the execute routine (0 xxxx 00, so ADD = 0, BRANCH = 4, STORE = 8, EXCHANGE = 12). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which are the fields of Mano's 20-bit microinstruction? A. OP, MODE, ADDR B. F1, F2, F3, CD, BR, AD C. F1, F2, CD, BR, AD, SBR D. A, B, C, D, E, F Answer: B. 3+3+3+2+2+7 = 20 bits. (Key point: Fields) 2. Why can up to three microoperations occur in one microinstruction? A. Because AD holds three operations B. Because BR repeats it three times C. F1, F2 and F3 each select one microoperation (000 = none) at the same time D. Because CD selects three registers Answer: C. Each 3-bit field is decoded separately. (Key point: Microoperation fields) 3. What register transfers does the fetch routine perform? A. AR<-PC; PC<-PC+1; AC<-DR B. DR<-PC; AR<-M[DR]; MAP C. IR<-PC; AR<-AC D. AR<-PC; DR<-M[AR], PC<-PC+1; AR<-DR(0-10) then MAP Answer: D. Three microinstructions at 64, 65, 66. (Key point: Fetch steps) 4. Where does the fetch routine start and how does it end? A. At address 64; ends with MAP to the opcode's routine B. At address 0; ends with RET C. At address 67; ends with CALL D. At address 64; ends with JMP to 64 Answer: A. MAP uses the opcode to find 0 xxxx 00. (Key point: Fetch address) ## Related in Computer Organization and Architecture - [Microinstruction format and microprogram design](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-fetch-indirect-add) — Computer Organization and Architecture, chapter 3 - [Steps in designing a microprogram control unit](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-design) — Computer Organization and Architecture, chapter 3 - [Microprogram control unit organization](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-control-org) — Computer Organization and Architecture, chapter 3, asked 2× - [Symbolic microprogram for fetch and add routines](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-fetch-add) — Computer Organization and Architecture, chapter 3 - [Microinstruction format](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroinstr-format) — Computer Organization and Architecture, chapter 3, asked 4× - [Why microprogrammed control is more flexible](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicro-vs-hardwired-flex) — Computer Organization and Architecture, chapter 3 ## Related in other subjects - [Hardwired vs microprogrammed control unit](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ahardwired-microprogrammed-cu) — Microprocessor, chapter 1, asked 3× - [Fetch and execution cycle with RTL](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Afetch-execute-cycle-rtl) — Microprocessor, chapter 1