---
title: "Microprogram control unit organization"
subject: "Computer Organization and Architecture"
chapter: 3
key: "semester_5/computer_organization_and_architecture:microprogram-control-org"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microprogram-control-org
site: BCT Engineering
---

# Microprogram control unit organization

Computer Organization and Architecture · Chapter 3: Control Unit

- Asked in: 2078 Bhadra, 10 marks; 2076 Asoj, 4 marks (asked 2 times)
- Video: [Microprogrammed Control Unit: Structure, Working, and Role in Computer Organization & Architecture](https://www.youtube.com/watch?v=5Sk5OpoT66E) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microprogram-control-org
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-3

## Question

Explain the organization structure of a microprogram control unit and the generation of control signals using microprogram.

## Short answer

A microprogrammed control unit stores microinstructions in a control memory (ROM). The CAR holds the next address, and a sequencer selects it from CAR+1, branch address, opcode mapping, or SBR return. The CDR feeds decoded microoperation fields to generate control signals.

## Answer

A microprogrammed control unit generates control signals by reading microinstructions from a control memory, instead of using fixed logic. Each machine instruction is carried out by a sequence of microinstructions (a microprogram or routine).

```text
 Instruction register (opcode)
          |
   +------v------+   +----------------+
   | Mapping     |-->|     CAR        |<-- next-address
   | logic       |   | (control addr) |    generator
   +-------------+   +-------+--------+    (sequencer)
                             |                  ^
                     +-------v--------+         |
                     |  Control memory|         | status,
                     |   (ROM)        |         | branch fields
                     +-------+--------+         |
                     +-------v--------+---------+
                     | Control data   |
                     | register (CDR) |
                     +-------+--------+
                             v
                  control signals to ALU, registers, buses
```

#### Components
- **Control memory (ROM):** stores the microprograms permanently. For Mano's computer it is 128 × 20 bits.
- **Control address register (CAR):** holds the address of the next microinstruction.
- **Sequencer (next-address logic):** selects CAR + 1, the branch address, the return address (from SBR) or the mapped address.
- **Control data register (pipeline register):** holds the microinstruction being executed, so that the next one can be fetched while it executes.
- **Mapping logic:** converts the opcode of the machine instruction to the starting address of its routine.
- **Subroutine register (SBR):** stores the return address for micro-subroutines.

#### Generation of control signals
1. The fetch routine is the first microprogram to run (CAR = 64). It loads the instruction into IR.
2. The opcode is mapped to the address of the routine for that instruction, and this address is loaded into CAR.
3. The microinstruction read from the control memory goes to the CDR. Its microoperation fields F1, F2, F3 are decoded by 3-to-8 decoders; each decoder output is a control signal (for example PCTAR, READ, INCPC) that enables a datapath transfer.
4. The CD, BR and AD fields go to the sequencer, which decides the next address.
5. At the end of the routine, a branch goes back to FETCH, and the cycle repeats.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How does a microprogrammed unit generate control signals?
   A. By fixed gates and flip-flops
   B. By the ALU
   C. By reading microinstructions from control memory
   D. By main memory data
   Answer: C. F1-F3 fields are decoded to give signals. (Key point: Control signals source)

2. What is the control data (pipeline) register for?
   A. Holds the next address
   B. Stores the opcode
   C. Stores return address
   D. Holds the microinstruction being executed so the next can be fetched meanwhile
   Answer: D. It allows overlap of fetch and execute of microinstructions. (Key point: CDR role)

3. How do F1, F2, F3 become control signals?
   A. 3-to-8 decoders; each output enables a datapath transfer
   B. They go to the CAR directly
   C. They are added by the ALU
   D. They are mapped to an address
   Answer: A. E.g. outputs such as PCTAR, READ, INCPC. (Key point: Decoders)

4. What happens at the end of an execute routine?
   A. Machine halts
   B. A branch goes back to FETCH
   C. CAR cleared and stays
   D. SBR is loaded with opcode
   Answer: B. The cycle then repeats. (Key point: Cycle)

## Related in Computer Organization and Architecture

- [Steps in designing a microprogram control unit](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-design) — Computer Organization and Architecture, chapter 3
- [Control signal types and hardware control unit](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acontrol-signals-hardware) — Computer Organization and Architecture, chapter 3
- [Organization of control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acontrol-memory-org) — Computer Organization and Architecture, chapter 3
- [Microprogram sequencer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-sequencer) — Computer Organization and Architecture, chapter 3, asked 5×
- [Symbolic microprogram for fetch and add routines](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-fetch-add) — Computer Organization and Architecture, chapter 3
- [Microinstruction format and fetch microprogram](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroinstr-format-fetch) — Computer Organization and Architecture, chapter 3, asked 2×

## Related in other subjects

- [Organizational structure and line organization](https://www.bctengineer.com/question.md?key=semester_7%2Forganization_and_management%3Aorg-structure-line) — Organization and Management, chapter 5
- [Org structure definition; line organization pros/cons](https://www.bctengineer.com/question.md?key=semester_7%2Forganization_and_management%3Aorg-structure-define-line) — Organization and Management, chapter 5
- [Short note: Organization structure](https://www.bctengineer.com/question.md?key=semester_7%2Forganization_and_management%3Ashort-note-org-structure) — Organization and Management, chapter 5
- [Entropy generation for a control mass](https://www.bctengineer.com/question.md?key=semester_2%2Ffundamental_of_thermodynamics_and_heat_transfer%3Aentropy-generation-control-mass) — Fundamental of Thermodynamics & Heat Transfer, chapter 5
