--- title: "Microinstruction format and microprogram design" subject: "Computer Organization and Architecture" chapter: 3 key: "semester_5/computer_organization_and_architecture:microprogram-fetch-indirect-add" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microprogram-fetch-indirect-add site: BCT Engineering --- # Microinstruction format and microprogram design Computer Organization and Architecture · Chapter 3: Control Unit - Asked in: 2069 Asar, 10 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microprogram-fetch-indirect-add - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-3 ## Question Design microinstruction format, symbolic and binary micro program that can perform fetch cycle, indirect cycle and add operation. Also design and describe the sequencing technique that is used in control unit. ## Short answer Fetch routine at address 64: PCTAR; READ,INCPC; DRTAR,MAP. ADD routine at 0: if I=1 CALL INDRCT; READ; ADD,JMP FETCH. Indirect routine at 67: READ; DRTAR,RET. Sequencing uses CAR+1, branch AD, opcode mapping, and SBR return. ## Answer #### Microinstruction format Use Mano's 20-bit format with a 128-word control memory (7-bit address). ```text | F1(3) | F2(3) | F3(3) | CD(2) | BR(2) | AD(7) | ``` - **F1, F2, F3:** microoperation fields. F1: 001 ADD (AC←AC+DR), 100 DRTAC, 101 DRTAR (AR←DR(0-10)), 110 PCTAR (AR←PC), 111 WRITE. F2: 100 READ (DR←M[AR]), 101 ACTDR, 111 PCTDR. F3: 101 INCPC (PC←PC+1), 110 ARTPC. - **CD:** 00 U (always true), 01 I (indirect bit DR(15)), 10 S (sign of AC), 11 Z (zero of AC). - **BR:** 00 JMP, 01 CALL, 10 RET, 11 MAP. - **AD:** branch address. #### Memory layout Fetch routine at 64, indirect routine at 67, ADD routine at 0 (opcode 0000 maps to 0 0000 00 = 0). #### Symbolic microprogram ```text ORG 0 ADD: NOP I CALL INDRCT ; if I = 1, do indirect READ U JMP NEXT ; DR <- M[AR] ADD U JMP FETCH ; AC <- AC + DR, go to fetch ORG 64 FETCH: PCTAR U JMP NEXT ; AR <- PC READ, INCPC U JMP NEXT ; DR <- M[AR], PC <- PC + 1 DRTAR U MAP ; AR <- DR(0-10), map opcode INDRCT: READ U JMP NEXT ; DR <- M[AR] DRTAR U RET ; AR <- DR(0-10), return ``` #### Binary microprogram | Address (dec / bin) | Label | Microoperations | CD | BR | AD | Binary F1 F2 F3 CD BR AD | |---|---|---|---|---|---|---| | 64 / 1000000 | FETCH | PCTAR | U | JMP | NEXT | 110 000 000 00 00 1000001 | | 65 / 1000001 | - | READ,INCPC | U | JMP | NEXT | 000 100 101 00 00 1000010 | | 66 / 1000010 | - | DRTAR | U | MAP | 0 | 101 000 000 00 11 0000000 | | 67 / 1000011 | INDRCT | READ | U | JMP | NEXT | 000 100 000 00 00 1000100 | | 68 / 1000100 | - | DRTAR | U | RET | 0 | 101 000 000 00 10 0000000 | | 0 / 0000000 | ADD | NOP | I | CALL | INDRCT | 000 000 000 01 01 1000011 | | 1 / 0000001 | - | READ | U | JMP | NEXT | 000 100 000 00 00 0000010 | | 2 / 0000010 | - | ADD | U | JMP | FETCH | 001 000 000 00 00 1000000 | (The AD field of MAP and RET is not used and is 0000000; the fetch routine ends with MAP so the opcode of DR chooses the next routine.) #### Sequencing technique The sequencer selects the next control address (CAR) from four sources: - **CAR + 1** when BR = JMP and the condition is false (or for sequential microinstructions), - **AD field** when BR = JMP or CALL and the condition (CD) is true, - **SBR** when BR = RET (return address saved by CALL), - **mapping logic** (0 + opcode + 00) when BR = MAP. ```text opcode -> map -+ AD field ------+--> MUX --> CAR --> Control memory SBR -----------+ ^ CAR+1 ---------------+ (select by CD, BR via branch logic) ``` Execution of ADD: fetch (64–66) loads AR and maps to address 0. At 0, if I = 1 (indirect) CALL INDRCT (67) saves return address 1 in SBR; INDRCT reads the effective address and RET goes back to address 1. At 1, DR ← M[AR]; at 2, AC ← AC + DR and the jump to FETCH starts the next instruction. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Where are fetch, indirect and ADD routines placed? A. Fetch 0, indirect 64, ADD 67 B. Fetch 64, indirect 67, ADD at 0 C. Fetch 64, indirect 0, ADD 67 D. All at 64 Answer: B. Opcode 0000 maps to address 0. (Key point: Layout) 2. How does ADD handle indirect addressing? A. JMP FETCH B. MAP C. NOP with I CALL INDRCT D. RET U Answer: C. If I = 1, INDRCT is called; RET returns to address 1. (Key point: Indirect handling) 3. What value is saved in SBR on the CALL at address 0? A. 0 B. 64 C. 67 D. 1 Answer: D. CAR+1 = 1. (Key point: Return address) 4. What does the ADD routine do in the last microinstruction? A. AC<-AC+DR then JMP to FETCH B. DR<-M[AR] C. AR<-PC D. MAP Answer: A. Address 2 jumps back to 64. (Key point: ADD execution) ## Related in Computer Organization and Architecture - [Microinstruction format and fetch microprogram](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroinstr-format-fetch) — Computer Organization and Architecture, chapter 3, asked 2× - [Symbolic microprogram for fetch and add routines](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-fetch-add) — Computer Organization and Architecture, chapter 3 - [Microinstruction fields and sequencing techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroinstr-fields-seq) — Computer Organization and Architecture, chapter 3 - [Steps in designing a microprogram control unit](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-design) — Computer Organization and Architecture, chapter 3 - [Microprogram control unit organization](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-control-org) — Computer Organization and Architecture, chapter 3, asked 2× - [Microinstruction format](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroinstr-format) — Computer Organization and Architecture, chapter 3, asked 4× ## Related in other subjects - [Fetch and execution cycle with RTL](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Afetch-execute-cycle-rtl) — Microprocessor, chapter 1