--- title: "Microprogram sequencer" subject: "Computer Organization and Architecture" chapter: 3 key: "semester_5/computer_organization_and_architecture:microprogram-sequencer" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microprogram-sequencer site: BCT Engineering --- # Microprogram sequencer Computer Organization and Architecture · Chapter 3: Control Unit - Asked in: 2079 Baisakh, 7 marks; 2078 Kartik, 6 marks; 2075 Asoj, 10 marks; 2074 Chaitra, 6 marks; 2070 Chaitra, 6 marks (asked 5 times) - Video: [Address Sequencing || Microprogram Sequencer || Computer Organization Architecture](https://www.youtube.com/watch?v=nxNytEYQLKI) — Sudhakar Atchala - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/microprogram-sequencer - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-3 ## Question Draw the block diagram of the microprogram sequencer for a control memory and explain its operations. ## Short answer The microprogram sequencer uses a multiplexer to select the next address from CAR+1, branch address field, SBR, or mapping logic. The CD field selects a status bit; the BR field and test condition determine the selection via input logic. For CALL, the return address is saved in SBR; for MAP, the opcode is mapped to a routine start address. ## Answer The microprogram sequencer is the part of the control unit that generates the address of the next microinstruction. It contains the next-address logic and CAR; together with the control memory, it forms the microprogrammed control unit. Mano's design has the following parts. ```text Instruction Status bits (I,S,Z) opcode (IR) | | +---v----+ +-----v-----+ | MUX 1 |<-- CD field (select) | Mapping | +---+----+ | logic | | +-----+-----+ +---v----------+ | | Input logic |<-- BR field | | (I0 I1 T) | | +---+----------+ | S1 S0 | L (load SBR) v v +--------------------------------+ AD -->| MUX 2 (selects address) |<-- SBR field | 0: CAR+1 1: branch (AD) | | 2: SBR 3: map | +---------------+----------------+ v +-----------+ +--------+ | CAR |-->| Control| +-----+-----+ | memory | | +---+----+ +-----v-----+ v | Incrementer| microinstruction +------------+ (to control data reg.) ``` #### Operation 1. The **CD field** selects one status bit (I, S, Z, or the constant 1) through MUX 1. The result is the signal T (test condition true). 2. The **BR field** (I1 I0) and T go to the **input logic**, which produces the select lines S1 S0 for MUX 2 and the load signal L for SBR: - JMP (00): S1S0 = 01 if T = 1 (branch to AD), S1S0 = 00 if T = 0 (increment). - CALL (01): same as JMP; in addition, when T = 1, L = 1 loads the return address (CAR + 1) into SBR. - RET (10): S1S0 = 10, selecting SBR. - MAP (11): S1S0 = 11, selecting the mapping logic. In Boolean form: S1 = I1, S0 = I1·I0 + I1'·T, L = I1'·I0·T. 3. **MUX 2** passes one of CAR + 1, the AD field, the SBR contents or the mapped address to CAR. 4. CAR addresses the control memory, which outputs the microinstruction into the control data register; its fields drive the datapath. 5. The incrementer forms CAR + 1, which is input 0 of MUX 2 and is the value stored in SBR during a CALL. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does the microprogram sequencer produce? A. The next address for the control memory (loaded into CAR) B. The control signals directly C. The operand from memory D. The instruction opcode Answer: A. Sequencer = next-address logic + CAR. (Key point: Role of the sequencer) 2. What is the job of MUX 1 and the CD field? A. CD selects the next address B. CD selects one status bit (I, S, Z or 1) to give the condition signal T C. CD selects the ALU function D. MUX 1 selects the SBR Answer: B. MUX 1 outputs T, the true-condition signal to the input logic. (Key point: MUX 1 and CD) 3. What outputs does the input logic generate from BR and T? A. The control data register contents B. The mapped address C. Select lines S1 S0 for MUX 2 and load signal L for SBR D. Only the AD field Answer: C. S1 S0 pick the address source and L saves the return address during CALL. (Key point: Input logic) 4. Which signals does MUX 2 select among? A. PC, IR, AR, DR B. CAR+1, ALU, AC, DR C. AD, opcode, flags, clock D. CAR+1, AD field, SBR, mapped address Answer: D. MUX 2 passes one of the four to CAR. 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