---
title: "Interconnection structures in multiprocessing"
subject: "Computer Organization and Architecture"
chapter: 8
key: "semester_5/computer_organization_and_architecture:multiprocessor-interconnection"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/multiprocessor-interconnection
site: BCT Engineering
---

# Interconnection structures in multiprocessing

Computer Organization and Architecture · Chapter 8: Multiprocessors

- Asked in: 2079 Baisakh, 4 marks; 2078 Bhadra, 4 marks; 2069 Chaitra, 4 marks (asked 3 times)
- Video: [Interconnection Structures in  Computer Organization Architecture](https://www.youtube.com/watch?v=_E5hCwzF6RM) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/multiprocessor-interconnection
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-8

## Question

Compare and contrast the interconnection structures used in multiprocessing environment.

## Short answer

Common bus is simple but limited; multiport memory allows several simultaneous accesses at high cost; crossbar provides non-blocking but is expensive; multistage networks offer scalable switching with possible blocking; hypercubes use direct links between neighbors for efficient routing.

## Answer

The processors, memory modules and I/O in a multiprocessor are connected by the following structures:

1. **Time-shared common bus:** one bus is shared by all modules; only one transfer at a time.
2. **Multiport memory:** each memory module has several ports, one per processor; priority resolves conflicts.
3. **Crossbar switch:** a switch at each crosspoint between processors and memory modules; many simultaneous transfers.
4. **Multistage switching network:** stages of 2×2 switches (omega network) between processors and memories.
5. **Hypercube:** 2ⁿ processors, each connected to n neighbours, differing by one address bit.

| Point | Common bus | Multiport memory | Crossbar | Multistage | Hypercube |
|---|---|---|---|---|---|
| Simultaneous transfers | One | Several (per module) | Maximum | Several, with blocking | Many links |
| Cost / hardware | Lowest | High (extra memory ports) | Highest, N² crosspoints | N/2 · log₂N switches | N · n/2 links |
| Contention | Highest | Memory conflicts | Only at the same memory | Possible path conflicts | Possible link conflicts |
| Scalability | Poor | Poor | Poor (cost) | Good | Good |
| Complexity | Simplest | Medium | Complex control | Routing logic | Routing by XOR |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many transfers can the time-shared common bus support at a time?
   A. Unlimited
   B. N
   C. One
   D. Two
   Answer: C. It has the highest contention and lowest cost. (Key point: Common bus)

2. How many crosspoints does an N x N crossbar need?
   A. N log N
   B. N
   C. 2N
   D. N^2
   Answer: D. Crossbar has N^2 crosspoints so it is costly. (Key point: Crossbar cost)

3. How many 2x2 switches does a multistage network use?
   A. N
   B. 2^N
   C. (N/2) log2 N
   D. N^2
   Answer: C. N/2 switches per stage and log2 N stages. (Key point: Multistage switches)

4. How is routing done in a hypercube?
   A. By a central bus
   B. By memory ports
   C. By random choice
   D. By XOR of source and destination addresses
   Answer: D. The 1 bits show the dimensions to travel. (Key point: Hypercube routing)

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