--- title: "Pipeline hazards and solutions" subject: "Computer Organization and Architecture" chapter: 4 key: "semester_5/computer_organization_and_architecture:pipeline-hazards" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/pipeline-hazards site: BCT Engineering --- # Pipeline hazards and solutions Computer Organization and Architecture · Chapter 4: Pipeline & Vector Processing - Asked in: 2078 Bhadra, 4+6 marks; 2076 Asoj, 2+4+2 marks; 2072 Chaitra, 6 marks; 2070 Asar, 2 marks; 2068 Chaitra, 10 marks (asked 5 times) - Video: [L-4.6: What is Hazard in Pipelining | various types of Hazards | computer Architecture](https://www.youtube.com/watch?v=srlgaJgaxRE) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/pipeline-hazards - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-4 ## Question What are the hazards in instruction pipelining? How can they be resolved? Explain. ## Short answer Pipeline hazards are structural (resource conflict), data (dependency), and control (branch). Solutions include separate memory for instruction/data to avoid structural hazards, operand forwarding or stalling for data hazards, and branch prediction or delayed branches for control hazards, improving throughput. ## Answer A hazard is a condition that prevents the next instruction in the pipeline from executing in its clock cycle, so the pipeline must stall and performance falls. #### Types of hazards and their solution **1. Structural (resource) hazard:** two instructions need the same hardware resource at the same time, for example both an instruction fetch and an operand fetch need the memory. - Solutions: separate instruction and data memories (caches), duplicate or pipeline the resource, add more ports, or stall one instruction. **2. Data hazard:** an instruction depends on the result of an earlier instruction that is not yet finished. Types: RAW (read after write, true dependency), WAR and WAW (name dependencies). Example: `ADD R1, R2, R3` followed by `SUB R4, R1, R5`; SUB needs R1 before ADD writes it. - Solutions: **operand forwarding (bypassing)** passes the ALU output directly to the next input; **hardware interlock** (stall) detects the dependency and delays the instruction; **compiler (software) scheduling** rearranges instructions or inserts NOPs; **delayed load**; register renaming for WAR/WAW. **3. Control (branch) hazard:** a branch changes the PC, so instructions already fetched after it may be wrong and must be discarded. - Solutions: **prefetch the target** (fetch both paths), **branch target buffer**, **branch prediction** (static or dynamic), **delayed branch** (compiler fills the slot after the branch with a useful instruction), **loop buffer**, and flushing the pipeline when the guess is wrong. ```text Time: 1 2 3 4 5 6 ADD R1,.. FI DA FO EX SUB .,R1 . FI DA -- FO EX <- stalled until R1 is ready ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Example of structural hazard? A. RAW on R1 B. Branch changes PC C. Instruction fetch and operand fetch both need memory D. Wrong prediction Answer: C. Fix: separate instruction/data memories. (Key point: Structural) 2. Fix that passes ALU output directly to next input? A. Delayed branch B. Loop buffer C. Branch target buffer D. Operand forwarding Answer: D. Bypassing. (Key point: Data hazard) 3. What is RAW? A. Read after write, a true dependency B. Write after read name dependency C. Write after write D. Read after read Answer: A. WAR and WAW are name dependencies. (Key point: RAW) 4. Which technique fills the slot after a branch with a useful instruction? A. Forwarding B. Delayed branch C. Interlock D. Register renaming Answer: B. Compiler fills the slot. (Key point: Control hazard) ## Related in Computer Organization and Architecture - [Four-segment instruction pipeline and space-time diagram](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Afour-segment-pipeline) — Computer Organization and Architecture, chapter 4, asked 5× - [Arithmetic and instruction pipeline](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aarith-instr-pipeline) — Computer Organization and Architecture, chapter 4, asked 2× - [Pipeline types and hazards](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Apipeline-types-hazards) — Computer Organization and Architecture, chapter 4 - [RISC and efficient instruction pipeline](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Arisc-pipeline) — Computer Organization and Architecture, chapter 4 - [Six-stage instruction pipeline](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Asix-stage-pipeline) — Computer Organization and Architecture, chapter 4 - [Pipeline and performance gain](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Apipeline-performance) — Computer Organization and Architecture, chapter 4 ## Related in other subjects - [Pipelining and multi-stage pipeline](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Apipelining-stages) — Embedded System, chapter 2, asked 3× - [Microwave radiation hazards based on radiation fields](https://www.bctengineer.com/question.md?key=semester_7%2Frf_and_microwave_engineering%3Aradiation-fields-hazards) — RF and Microwave Engineering, chapter 7, asked 2× - [Main geohazards versus man-made hazards](https://www.bctengineer.com/question.md?key=semester_4%2Fengineering_geology_ii%3Amain-geohazards-manmade) — Engineering Geology II, chapter 5, asked 2× - [Emission hazards and health impact](https://www.bctengineer.com/question.md?key=semester_7%2Fenergy_environment_and_society%3Aemission-hazard-health-impact) — Energy Environment and Society, chapter 4, asked 2×