---
title: "Types of priority interrupt"
subject: "Computer Organization and Architecture"
chapter: 7
key: "semester_5/computer_organization_and_architecture:priority-interrupt"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/priority-interrupt
site: BCT Engineering
---

# Types of priority interrupt

Computer Organization and Architecture · Chapter 7: Input-Output Organization

- Asked in: 2072 Kartik, 4 marks
- Video: [Priority interrupts | COA | Lec-34 | Bhanu Priya](https://www.youtube.com/watch?v=Y3rT6tkM8kc) — Education 4u
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/priority-interrupt
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-7

## Question

What are the different types of priority interrupt?

## Short answer

The three types are software polling (testing devices in priority order), daisy chaining (serial priority where the first requesting device on the interrupt acknowledge line supplies its vector), and parallel priority (using interrupt register, mask register, and priority encoder to select the highest‑priority unmasked request).

## Answer

A priority interrupt system decides which interrupt is served first when several devices request service at the same time. The three types are:

1. **Software polling (polling):** on any interrupt, a single branch address starts a polling routine that tests each device's status flag in priority order. The first device found with its flag set is serviced. It is simple and needs little hardware, but it is slow because identifying the device takes a long time.
2. **Daisy chaining (serial priority):** all devices share one interrupt request line. The interrupt acknowledge signal passes through the devices in series, starting from the highest-priority one. The first requesting device blocks the signal and puts its vector address on the data bus. It is cheap, but a failure breaks the chain and low-priority devices may starve.
3. **Parallel priority:** each device has its own bit in an **interrupt register** and a bit in a **mask register**. A priority encoder selects the highest-priority unmasked request and generates its vector address. It is fast and flexible (masking) but needs more hardware.

```text
 Daisy chain:
 CPU INTACK -> [Dev1 PI/PO] -> [Dev2] -> [Dev3] -> ...
 Interrupt request line (common, wired OR) <- all devices

 Parallel priority:
 Dev0..Dev3 -> Interrupt reg & Mask reg -> Priority encoder
                                             -> vector (x y) -> CPU
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which are the three types of priority interrupt?
   A. Vector, scalar and array
   B. Daisy chaining, DMA and cycle stealing
   C. Polling, daisy chaining and parallel priority
   D. Polling, DMA and IOP
   Answer: C. The three types are software polling, daisy chaining and parallel priority. (Key point: Types)

2. How does software polling find the interrupting device?
   A. The acknowledge signal passes through devices
   B. A priority encoder outputs its vector
   C. The device writes its name to disk
   D. A common routine tests each device's status flag in priority order
   Answer: D. A single branch address starts a routine that checks flags in priority order; the first set flag is serviced. (Key point: Polling)

3. What is a drawback of daisy chaining?
   A. It has no priority
   B. It cannot use vector addresses
   C. It needs a lot of hardware
   D. A failure breaks the chain and low-priority devices may starve
   Answer: D. It is cheap, but a broken link affects all devices after it, and low priority devices may never be served. (Key point: Daisy chain weakness)

4. Why is parallel priority flexible?
   A. It needs no hardware
   B. It serves all devices at once
   C. It uses a mask register so chosen interrupts can be disabled
   D. It uses only polling
   Answer: C. Each device has a mask bit, allowing selective masking; but it needs more hardware. (Key point: Parallel priority advantage)

## Related in Computer Organization and Architecture

- [I/O module functions and priority interrupt](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aio-module-priority-interrupt) — Computer Organization and Architecture, chapter 7, asked 3×