---
title: "Limitations of single bus system"
subject: "Computer Organization and Architecture"
chapter: 1
key: "semester_5/computer_organization_and_architecture:single-bus-limit"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/single-bus-limit
site: BCT Engineering
---

# Limitations of single bus system

Computer Organization and Architecture · Chapter 1: Introduction

- Asked in: 2075 Chaitra, 2 marks; 2072 Chaitra, 2 marks (asked 2 times)
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/single-bus-limit
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-1

## Question

Discuss the limitations of using a single bus system to connect different devices in any given system.

## Short answer

A single bus limits bandwidth because only one transfer occurs at a time, causing slow devices to delay fast ones. Its length and load increase propagation delay. Arbitration adds overhead, and a bus failure stops the whole system, so scalability is limited.

## Answer

A single bus connects the CPU, memory and all I/O devices to one shared set of lines. It is simple and cheap, but it has these limitations:

1. **Bandwidth bottleneck:** only one transfer can happen at a time. When many devices compete, they must wait, and overall speed falls.
2. **Speed mismatch:** fast devices (CPU, memory) must share the bus with slow devices (keyboard, printer), so the bus is held up by the slowest devices.
3. **Propagation delay:** as more devices are attached, the bus gets longer and has more capacitive load, so signals take longer and the clock must be slower.
4. **Arbitration overhead:** the bus must be granted to one device for every transfer, which adds delay and needs extra control hardware.
5. **Single point of failure:** if the bus fails, the whole system stops.
6. **Limited scalability:** beyond a certain point, adding devices reduces performance instead of improving it.

These problems are reduced by using a **bus hierarchy** with separate local, system and expansion buses joined by bridges.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why does a single bus become a bottleneck?
   A. It has too many data lines
   B. It cannot carry control signals
   C. It only supports slow devices
   D. Only one transfer can occur at a time, so devices must wait
   Answer: D. All devices share the same lines, so concurrent transfers are impossible. (Key point: Bandwidth bottleneck)

2. How does adding more devices affect a single bus?
   A. The bus becomes faster because of more drivers
   B. The bus gets longer with more load, so signals are slower and the clock must slow down
   C. Nothing changes in timing
   D. Only the cost drops
   Answer: B. Longer lines and more capacitive load increase propagation delay. (Key point: Propagation delay)

3. How are single-bus problems reduced?
   A. By removing the slow devices
   B. By adding more I/O devices to the same bus
   C. By removing arbitration
   D. By using a bus hierarchy with bridges
   Answer: D. Separate local, system and expansion buses joined by bridges reduce the load and mismatch. (Key point: Remedy)

## Related in Computer Organization and Architecture

- [Data bus and address bus width](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Abus-widths) — Computer Organization and Architecture, chapter 1, asked 2×
- [Bus structure of a typical computer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Abus-structure) — Computer Organization and Architecture, chapter 1

## Related in other subjects

- [FACTS devices changing the power system](https://www.bctengineer.com/question.md?key=semester_8%2Fhigh_voltage_engineering%3Afacts-changes-power-system) — High Voltage Engineering, chapter 1
- [Interconnected system SLD with bus voltages](https://www.bctengineer.com/question.md?key=semester_4%2Fpower_system_analysis_i%3Ainterconnected-sld-bus-voltages) — Power System Analysis I, chapter 1
- [Microprocessor based system and bus organization](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amp-based-system-bus-organization) — Microprocessor, chapter 1, asked 5×
- [Reactance diagram of eight-bus system](https://www.bctengineer.com/question.md?key=semester_4%2Fpower_system_analysis_i%3Areactance-diagram-eight-bus) — Power System Analysis I, chapter 3
