---
title: "Tightly-coupled multiprocessor"
subject: "Computer Organization and Architecture"
chapter: 8
key: "semester_5/computer_organization_and_architecture:tightly-coupled"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/tightly-coupled
site: BCT Engineering
---

# Tightly-coupled multiprocessor

Computer Organization and Architecture · Chapter 8: Multiprocessors

- Asked in: 2076 Asoj, 4 marks
- Video: [What is tightly coupled multiprocessors | Types of tightly coupled multiprocessors](https://www.youtube.com/watch?v=dER7hTm3IGg) — Chirag Bhalodia
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/tightly-coupled
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-8

## Question

Discuss tightly-coupled multiprocessors with block diagram.

## Short answer

Processors share a common memory and I/O through an interconnection network; each may have a cache. Communication is fast via shared memory, but memory contention and cache coherence limit scalability.

## Answer

A tightly coupled multiprocessor has several processors that share a common global memory and I/O channels and are controlled by one operating system. Processors communicate through the shared memory, so the data rate is high and the delay is low.

```text
  +-------+  +-------+       +-------+
  | CPU 1 |  | CPU 2 |  ...  | CPU n |
  +-------+  +-------+       +-------+
  | cache |  | cache |       | cache |
  +---+---+  +---+---+       +---+---+
      |          |               |
  ==============================================
        Interconnection network (bus / crossbar /
        multistage / multiport memory)
  ==============================================
      |            |             |
  +---v---+    +---v---+     +---v---+
  |Memory |    |Memory |     |  I/O  |
  |  M1   | ...|  Mk   |     | chan. |
  +-------+    +-------+     +-------+
```
- Each processor may have a local cache or memory to cut bus traffic, and the shared memory is made up of several modules.
- Processors, shared memory and I/O are connected by a common bus, crossbar switch or multiport memory.
- **Merits:** fast interprocessor communication, simple programming model, high data rate.
- **Demerits:** memory contention and bus bottleneck, cache coherence problems, poor scalability.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What best defines a tightly coupled multiprocessor?
   A. Several processors, each with only private memory, linked by message-passing over a network
   B. Several processors sharing a common global memory and I/O channels under one operating system
   C. Several independent computers each running its own operating system
   D. A single processor with multiple pipelines and no shared memory
   Answer: B. Tightly coupled systems share global memory and I/O channels and are controlled by a single operating system. (Key point: Definition of tightly coupled)

2. How do processors communicate in a tightly coupled multiprocessor?
   A. By sending messages over a LAN
   B. By exchanging data through the shared memory
   C. By copying files between local disks
   D. By direct serial links between each pair of CPUs
   Answer: B. Communication takes place through shared memory, giving high data rate and low delay. (Key point: Communication mechanism)

3. Why may each processor in the block diagram have a local cache or memory?
   A. To reduce traffic on the common bus / interconnection network
   B. To remove the need for shared memory
   C. To allow each CPU to run a separate operating system
   D. To increase the number of I/O channels
   Answer: A. Local cache cuts bus traffic, easing the bus bottleneck, though it introduces cache coherence problems. (Key point: Role of local cache)

4. Which is a demerit of tightly coupled multiprocessors?
   A. Slow interprocessor communication
   B. Complex message-passing programming model
   C. Memory contention, bus bottleneck, cache coherence problems and poor scalability
   D. Low data rate between processors
   Answer: C. Sharing memory and bus causes contention and coherence issues, limiting scalability; its merits are fast communication and simple programming. (Key point: Demerits)

## Related in Computer Organization and Architecture

- [Tightly vs loosely coupled multiprocessors](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Atight-loose-coupled) — Computer Organization and Architecture, chapter 8, asked 3×