--- title: "Vector processing and pipelining performance" subject: "Computer Organization and Architecture" chapter: 4 key: "semester_5/computer_organization_and_architecture:vector-pipeline-performance" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/vector-pipeline-performance site: BCT Engineering --- # Vector processing and pipelining performance Computer Organization and Architecture · Chapter 4: Pipeline & Vector Processing - Asked in: 2079 Baisakh, 10 marks; 2069 Chaitra, 10 marks (asked 2 times) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/vector-pipeline-performance - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-4 ## Question What is vector processing? How does pipelining improve the performance of a computer? Explain with example. ## Short answer Vector processing applies a single instruction to arrays of data, avoiding loop overhead. Pipelining improves performance by overlapping execution: with k segments and n tasks, pipelined time = (k+n-1)tp. For k=4, tp=20ns, n=100, speedup = (100×4×20)/(103×20) = 3.88. ## Answer #### Vector processing Vector processing is the processing of vectors (one-dimensional arrays of data) by a single instruction that operates on all the elements. It avoids the loop overhead of scalar code and uses pipelined functional units. A vector instruction specifies the operation, the base addresses of the operands and the result, and the vector length: `C(1:100) = A(1:100) + B(1:100)` is one instruction, instead of a loop of 100 iterations with an index increment, test and branch each time. It is used in weather forecasting, seismic analysis, image processing and simulation (for example, Cray supercomputers). A vector processor has vector registers, pipelined arithmetic units and interleaved memory banks that can supply one element per clock. #### How pipelining improves performance A pipeline of k segments with clock time tp can finish one task per clock after the first one. For n tasks: - Non-pipelined time = n · tn, where tn = k · tp - Pipelined time = (k + n - 1) · tp - **Speedup S = n · k · tp / ((k + n - 1) · tp) = n·k / (k + n - 1)**, which tends to k as n becomes large. Example: k = 4 segments, tp = 20 ns, n = 100 tasks. - Non-pipelined: 100 × 4 × 20 = 8000 ns - Pipelined: (4 + 100 - 1) × 20 = 103 × 20 = 2060 ns - Speedup = 8000 / 2060 = **3.88** (close to k = 4). - Throughput rises from 1 task per 80 ns to about 1 per 20 ns. For six tasks on 4 segments: S = (6 × 4) / (4 + 6 - 1) = 24/9 = 2.67 (see the space-time diagram below). ```text Segment | 1 2 3 4 5 6 7 8 9 ------------------------------------ S1 | T1 T2 T3 T4 T5 T6 . . . S2 | . T1 T2 T3 T4 T5 T6 . . S3 | . . T1 T2 T3 T4 T5 T6 . S4 | . . . T1 T2 T3 T4 T5 T6 ``` Pipelining raises throughput without making a single task faster; hazards (branches, dependencies) reduce the gain. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why is C(1:100) = A(1:100) + B(1:100) as one vector instruction faster than a scalar loop? A. It uses a faster clock B. It avoids repeating index increment, test and branch for each element C. It uses fewer data elements D. It removes the need for memory Answer: B. The scalar loop has overhead (index increment, test, branch) on each of 100 iterations; the vector instruction carries base address, length and operation once. (Key point: Vector instruction advantage) 2. Which set of hardware lets a vector processor supply one element per clock? A. Vector registers, pipelined arithmetic units and interleaved memory banks B. A single large cache and a hardwired control unit C. Multiple instruction streams and shared buses only D. A microprogrammed control unit and a stack Answer: A. Pipelined units compute one element per clock while interleaved banks feed data fast enough. (Key point: Vector processor components) 3. For n tasks on a k-segment pipeline, what is the speedup? A. n / (k + n - 1) B. k / (n + k - 1) C. n·k / (k + n - 1) D. (k + n - 1) / (n·k) Answer: C. Non-pipelined time is n·k·tp and pipelined time is (k + n - 1)·tp, so S = n·k/(k + n - 1). (Key point: Speedup formula) 4. For k = 4, tp = 20 ns and n = 100 tasks, what are the pipelined time and speedup? A. 8000 ns and 1.0 B. 2060 ns and 3.88 C. 2000 ns and 4.00 D. 2080 ns and 3.85 Answer: B. Pipelined time = (4 + 100 - 1) x 20 = 2060 ns; non-pipelined = 8000 ns; speedup = 8000/2060 = 3.88. (Key point: Numerical example) 5. What does pipelining improve, and what reduces its gain? A. It makes a single task faster; hazards have no effect B. It raises throughput without making one task faster; hazards reduce the gain C. It lowers throughput but cuts latency; branches improve it D. It reduces the number of tasks; clock time reduces gain Answer: B. A single task still takes k clocks; pipelining raises throughput, but branches and dependencies cause stalls. (Key point: Limits of pipelining) ## Related in Computer Organization and Architecture - [Parallel processing and pipelining](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aparallel-processing) — Computer Organization and Architecture, chapter 4 - [Vector computation for performance](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Avector-computation) — Computer Organization and Architecture, chapter 4 - [Data dependency problem in pipelining](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adata-dependency) — Computer Organization and Architecture, chapter 4 - [Pipeline and performance gain](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Apipeline-performance) — Computer Organization and Architecture, chapter 4 - [Types of array processing](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aarray-processing) — Computer Organization and Architecture, chapter 4 - [Performance balance and bus design elements](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aperf-balance-bus-design) — Computer Organization and Architecture, chapter 1, asked 2× ## Related in other subjects - [Computer image processing with example](https://www.bctengineer.com/question.md?key=semester_8%2Fmultimedia_system%3Acomputer-image-processing) — Multimedia System, chapter 3 - [Recommendations to improve your college](https://www.bctengineer.com/question.md?key=semester_7%2Forganization_and_management%3Acollege-improvement-recommendations) — Organization and Management, chapter 9 - [Stored program concept and processing cycle](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Astored-program-processing-cycle) — Microprocessor, chapter 1, asked 6× - [Improving seismic performance of masonry](https://www.bctengineer.com/question.md?key=semester_5%2Fconcrete_technology_and_masonry_structure%3Aseismic-performance-improvement) — Concrete Technology and Masonry Structure, chapter 9