---
title: "Need for IOP and DMA control"
subject: "Computer Organization and Architecture"
chapter: 7
key: "semester_5/computer_organization_and_architecture:why-iop-dma"
source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/why-iop-dma
site: BCT Engineering
---

# Need for IOP and DMA control

Computer Organization and Architecture · Chapter 7: Input-Output Organization

- Asked in: 2073 Chaitra, 10 marks
- Video: [Input output processor IOP |  IOP and DMA Communication | COA Lecture series](https://www.youtube.com/watch?v=dlCi4ymj2Vs) — LS Academy for Technical Education 
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/why-iop-dma
- Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-7

## Question

Why is an I/O processor necessary in an input-output organization? Explain about DMA control with necessary diagram.

## Short answer

An I/O processor is needed to offload I/O from the CPU, executing I/O programs for complex operations while the CPU runs computations; a DMA controller only handles simple block transfers. DMA control uses address, word count, and control registers, asserting bus request to take over the bus and transfer data directly between device and memory, interrupting the CPU upon completion.

## Answer

#### Need for an I/O processor
An input-output processor (IOP) is a processor with its own instruction set and control unit that handles all I/O transfers, so the CPU is free for computation. It is needed because:

- With programmed or interrupt-driven I/O, the CPU is busy during every transfer or interrupt, and the system slows down when there are many devices.
- A single DMA controller handles only simple block transfers. An IOP can do more: format conversion, error checking, code conversion, and chained transfers described by an I/O program.
- Devices differ in speed, word format and control. The IOP hides these differences and gives the CPU one simple interface.
- The IOP works in parallel with the CPU, so overall throughput and CPU utilisation rise.
- Many peripherals can be attached to one IOP (a channel), which reduces the load on the CPU and the system bus.

```text
        +---------+          +-------------------+
        | Memory  |<-------->|   Memory bus      |
        |  unit   |          +----+---------+----+
        +---------+               |         |
                              +---v---+  +--v----+
                              |  CPU  |  |  IOP  |
                              +-------+  +--+----+
                                            | I/O bus
                          +---------+-------+---------+
                          v         v                 v
                      Keyboard    Printer           Disk
                                  (peripherals)
```

#### DMA control

DMA control lets an I/O device transfer data directly to or from memory without the CPU handling every word. The DMA controller has an address register, a word count register and a control register, with BR/BG lines for the bus.

```text
                          +---------------------+
   Address bus  <-------->| Address register    |
   Data bus     <-------->| Word count register |
                          | Control register    |
                          +---------------------+
   DS (DMA select) ------>|                     |
   RS (reg. select) ----->|                     |
   RD (read)    <-------->|    Control logic    |
   WR (write)   <-------->|                     |<---- DMA request (from I/O device)
   BR (bus request) <-----|                     |----> DMA acknowledge (to I/O device)
   BG (bus grant) ------->|                     |
   Interrupt    <---------|                     |
                          +---------------------+
```
- **Address register:** holds the memory address of the next word to transfer; it increments after each word.
- **Word count register:** holds the number of words left; it decrements after each word. When it reaches zero, the transfer is finished and an interrupt is sent to the CPU.
- **Control register:** sets the mode of transfer (read or write, burst or cycle stealing).
- **DS, RS (DMA select, register select):** the CPU uses them with RD/WR to program the three registers through the data bus.
- **BR, BG:** the DMA controller asks the CPU for the buses with BR; the CPU grants them with BG and puts its address, data and control lines in the high-impedance state.
- **DMA request / acknowledge:** handshake lines with the I/O device.

#### Steps in a DMA transfer

1. **Initialisation by CPU:** the CPU writes the starting memory address, the word count and the transfer direction into the DMA controller, and starts the device. The CPU then continues with other work.
2. **DMA request:** when the peripheral has data ready, it sends a DMA request to the controller.
3. **Bus request:** the controller sends BR to the CPU.
4. **Bus grant:** the CPU finishes its current bus cycle, floats its buses and replies with BG.
5. **Acknowledge:** the controller sends DMA acknowledge to the device and places the contents of the address register on the address bus.
6. **Transfer:** one word moves directly between the device and memory (the controller drives the read or write signal). The address register is incremented and the word count is decremented.
7. **Repeat or release:** in burst mode, the controller keeps the bus until the whole block is done; in cycle-stealing mode, it releases the bus after every word.
8. **Completion:** when the word count becomes zero, the controller drops BR and interrupts the CPU. The CPU then takes back control and checks the status.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why is an IOP better than a single DMA controller?
   A. It has its own instruction set and can do format conversion, error checking and chained transfers
   B. It handles only simple block transfers
   C. It has no control unit
   D. It is cheaper
   Answer: A. A DMA controller does simple block transfers, while an IOP runs I/O programs with extra functions. (Key point: Why an IOP)

2. What happens when the word count register of the DMA controller reaches zero?
   A. The transfer is finished and an interrupt is sent to the CPU
   B. The address register is cleared and nothing else happens
   C. The transfer restarts
   D. The CPU is halted permanently
   Answer: A. Zero count means the block is done; the controller drops BR and interrupts the CPU. (Key point: Word count register)

3. What does the CPU do when it receives BR from the DMA controller?
   A. Ignores it
   B. Resets itself
   C. Sends data to the device
   D. Finishes its current bus cycle, floats its buses and replies with BG
   Answer: D. The CPU completes the current cycle, tri-states address, data and control lines, and grants the bus. (Key point: Bus request and grant)

4. What does the CPU write into the DMA controller at the start of a transfer?
   A. The starting memory address, the word count and the direction
   B. The interrupt vector table
   C. The BIOS
   D. The device driver
   Answer: A. The CPU programs the address, count and control registers, then continues other work. (Key point: CPU initialisation)

## Related in Computer Organization and Architecture

- [Need for I/O processor (IOP)](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Awhy-iop) — Computer Organization and Architecture, chapter 7, asked 5×
- [DMA controller block diagram and transfer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-controller) — Computer Organization and Architecture, chapter 7, asked 6×
- [CPU and IOP communication](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acpu-iop-communication) — Computer Organization and Architecture, chapter 7, asked 2×
- [Microprogram control unit organization](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amicroprogram-control-org) — Computer Organization and Architecture, chapter 3, asked 2×
- [Organization of control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acontrol-memory-org) — Computer Organization and Architecture, chapter 3

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