--- title: "Write policy; direct vs associative mapping" subject: "Computer Organization and Architecture" chapter: 6 key: "semester_5/computer_organization_and_architecture:wp-direct-vs-assoc" source: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/wp-direct-vs-assoc site: BCT Engineering --- # Write policy; direct vs associative mapping Computer Organization and Architecture · Chapter 6: Memory System - Asked in: 2079 Baisakh, 8 marks - Video: [Cache Memory Mapping – A Comparative Study](https://www.youtube.com/watch?v=e8RCnG2ibJk) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/computer_organization_and_architecture/wp-direct-vs-assoc - Whole chapter: https://www.bctengineer.com/md/semester_5/computer_organization_and_architecture/chapter-6 ## Question What do you mean by write policy? Discuss and differentiate direct mapping and associative mapping functions in cache design. ## Short answer Write policy determines when main memory is updated on a CPU write: write-through updates both cache and memory immediately; write-back updates only cache and sets a dirty bit, writing back on replacement. Direct mapping assigns each block to one fixed line (block mod lines), simple but causes thrashing. Associative mapping allows any block in any line, uses parallel tag comparison, eliminates thrashing, but requires many comparators and a replacement algorithm. ## Answer #### Write policy When the CPU writes to a cached word, the cache and main memory may become different. The write policy decides when main memory is updated. 1. **Write-through:** every write goes to both the cache and main memory at once. Memory is always up to date and the design is simple, but write traffic is high and the CPU may wait for the slow memory (a write buffer reduces this). 2. **Write-back (copy-back):** a write updates only the cache and sets a **dirty bit** on the line. Main memory is updated only when the line is replaced. Writes are fast and the bus traffic is low, but memory is temporarily stale and the control is more complex (important in multiprocessors). 3. **Write-once:** the first write to a block is written through (to tell other caches), later writes are write-back. It is used for cache coherence in multiprocessor systems. On a write miss the cache uses either **write-allocate** (load the block, then write) or **no-write-allocate** (write directly to memory). #### Direct mapping ```text Address (16 bits) +-----------+---------+--------+ | Tag 10b | Line 4b | Word 2b| +-----+-----+----+----+--------+ | | | +-----v------+ | | line 0 | tag | data | | line 1 | tag | data | | ... | | | line 15 | tag | data | +-----+------+ v v +--------------------+ | compare tag = ? |--> hit / miss +--------------------+ ``` Working: the line field selects one line, and the tag stored there is compared with the tag of the address. If the tags are equal (and the valid bit is set), it is a **hit**, and the word field picks the word. Otherwise it is a **miss**: the block is read from memory into that line, and the line's tag is updated. Example: blocks 0, 16, 32 of main memory all map to line 0 (block mod 16); block 5 maps to line 5; block 21 also maps to line 5. - **Merits:** simple and cheap hardware (only one comparator), fast lookup, no replacement algorithm needed. - **Demerits:** fixed location for each block, so two blocks that map to the same line keep replacing each other (thrashing) even when other lines are empty; lower hit ratio. #### Associative (fully associative) mapping A main-memory block can be placed in **any** cache line. The address is split into **Tag | Word**; the tag is the full block number. ```text Address (16 bits) +----------------------+--------+ | Tag 14b | Word 2b| +----------+-----------+--------+ | compare with ALL tags in parallel +------+-----------+------+ | line0| tag0 | data |--= ? | line1| tag1 | data |--= ? | ... | ... | ... |--= ? +------+-----------+------+--> hit / miss ``` Working: the tag is compared with the tags of all lines at the same time (associative or content-addressable memory). A match is a hit. On a miss the block is loaded into any free line; if the cache is full, a **replacement algorithm** (LRU, FIFO, LFU, random) chooses the line to remove. Example: with 16 lines, blocks 0, 16, 32 and 5 can all stay in the cache together, because any line can hold any block. - **Merits:** most flexible, best hit ratio, no thrashing. - **Demerits:** needs one comparator per line (costly, slow, more power), long tag, and a replacement algorithm. #### Difference between direct and associative mapping | Point | Direct | Associative | |---|---|---| | Block placement | Only one fixed line | Any line | | Address fields | Tag, line, word | Tag, word | | Comparators | One | One per line | | Replacement algorithm | Not needed | Needed | | Hit ratio | Lower (conflicts) | Higher | | Cost, speed | Cheap, fast | Costly, slower | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In write-back, when is main memory updated? A. On every write B. When a dirty line is replaced C. Never D. At the first read Answer: B. A dirty bit marks modified lines, written back at replacement. (Key point: Write-back) 2. Which fields does direct mapping use? A. Tag, Word B. Tag, Line, Word C. Set, Word D. Line only Answer: B. Line selects the single line. (Key point: Direct address) 3. How many comparators are used in direct versus associative mapping? A. One versus one per line B. One per line versus one C. Two versus four D. None versus one Answer: A. Direct mapping checks only one line; associative checks all in parallel. (Key point: Comparators) 4. Which needs a replacement algorithm? A. Direct only B. Associative only C. Both D. Neither Answer: B. Direct has a single fixed line; associative must choose a victim. (Key point: Replacement) ## Related in Computer Organization and Architecture - [Cache management; direct vs associative address structure](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-vs-assoc-address) — Computer Organization and Architecture, chapter 6 - [Associative cache mapping with example](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aassoc-cache-example) — Computer Organization and Architecture, chapter 6 - [Cache read and direct-mapping demerits](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-demerits) — Computer Organization and Architecture, chapter 6 - [Direct cache mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping) — Computer Organization and Architecture, chapter 6, asked 3× - [Direct mapping with 32-block memory, 8-block cache](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example) — Computer Organization and Architecture, chapter 6, asked 3× - [Cache mapping techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acache-mapping-techniques) — Computer Organization and Architecture, chapter 6, asked 7× ## Related in other subjects - [Associative cache mapping](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aassociative-cache-mapping) — Embedded System, chapter 4, asked 2× - [Cache memory mapping techniques](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-mapping-techniques) — Embedded System, chapter 4, asked 3× - [Cache write policy and replacement algorithm](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-write-policy-replacement) — Embedded System, chapter 4