--- title: "Why simulate resistors with switched capacitors in MOS" subject: "Filter Design" chapter: 9 key: "semester_5/filter_design:sc-resistor-simulation-mos" source: https://www.bctengineer.com/q/semester_5/filter_design/sc-resistor-simulation-mos site: BCT Engineering --- # Why simulate resistors with switched capacitors in MOS Filter Design · Chapter 9: Switched-Capacitor Filters - Asked in: 2080 Baisakh, 2+4 marks - Video: [Analog VLSI: Resistor Realization Using Switched Capacitor](https://www.youtube.com/watch?v=Jv-JEu0CJ8s) — Electronics Practice - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/filter_design/sc-resistor-simulation-mos - Whole chapter: https://www.bctengineer.com/md/semester_5/filter_design/chapter-9 ## Question Why do we need switched capacitor to simulate resistor in MOS technology? How can you simulate a resistor using switched capacitor? Explain with necessary derivations. ## Short answer MOS resistors of MΩ range are too large and inaccurate; switched capacitors give area-efficient, accurate, tunable resistance dependent only on capacitor ratio and clock. A capacitor C switched at frequency fc between two nodes using non-overlapping clocks transfers charge C(V1-V2) each period, yielding average current fc C(V1-V2) and equivalent resistance Req = 1/(fc C). ## Answer #### Need for switched capacitors in MOS technology Active-RC filters for audio and voice frequencies need resistors of hundreds of kΩ to MΩ, which MOS ICs cannot provide well: - **Chip area:** diffused or poly resistors have low sheet resistance, so a 1 MΩ resistor occupies a very large area; a switched capacitor giving 10 MΩ needs only about 1 pF. - **Accuracy:** absolute values of on-chip R and C vary by about ±20 %, and the errors are independent, so the RC time constant may be off by ±40 %. With SC, the time constant becomes $\tau = C/(f_cC_R)$, which depends only on a **capacitor ratio** (accurate to about 0.1 % in MOS) and a crystal clock. - **Temperature and linearity:** capacitor ratios track with temperature and voltage; diffused resistors do not. - **Tunability:** changing the clock frequency moves all pole and zero frequencies together. - MOS gives near-ideal switches (very high off resistance) and op-amps with high input impedance that hold charge, so SC circuits are natural in MOS. #### Simulating a resistor with a switched capacitor (parallel type) Consider a capacitor $C_R$ with two MOS switches driven by non-overlapping clocks $\phi_1$ and $\phi_2$ of frequency $f_c = 1/T_c$: ```text phi1 phi2 V1 ----o/o----+----o/o---- V2 | === CR | GND ``` 1. **Phase $\phi_1$** (left switch closed): $C_R$ charges to $V_1$; stored charge $q_1 = C_RV_1$. 2. **Phase $\phi_2$** (right switch closed): $C_R$ charges/discharges to $V_2$; stored charge $q_2 = C_RV_2$. 3. Charge moved from node 1 to node 2 in one clock period: $$ \Delta q = q_1 - q_2 = C_R(V_1 - V_2) $$ 4. If $f_c$ is much higher than the signal frequency, $V_1$ and $V_2$ are nearly constant over a period, so the average current is $$ \begin{aligned} I_{avg} &= \frac{\Delta q}{T_c} = C_Rf_c(V_1 - V_2) \\ R_{eq} &= \frac{V_1 - V_2}{I_{avg}} = \frac{1}{f_cC_R} = \frac{T_c}{C_R} \end{aligned} $$ So a capacitor switched at rate $f_c$ behaves like a resistor $R_{eq} = 1/(f_cC_R)$. Example: $C_R = 1$ pF, $f_c = 100$ kHz gives $R_{eq} = 10$ MΩ. **Other forms:** the series switched capacitor gives the same $R_{eq} = 1/(f_cC_R)$, and the bilinear type gives $R_{eq} = 1/(4f_cC_R)$. **Conditions:** two-phase non-overlapping clock (so the nodes are never shorted together), $f_c \gg$ highest signal frequency (typically 50–100 times), and the nodes are driven by low-impedance sources such as op-amp outputs or virtual ground. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why does an SC time constant beat an on-chip RC time constant? A. On-chip resistors are perfectly linear B. It depends on a capacitor ratio and the clock, not on absolute R and C that vary about ±20 % C. It uses a lower clock frequency D. It needs no capacitor Answer: B. τ = C/(fc·CR) depends only on a capacitor ratio (about 0.1 % accurate) and a crystal clock. (Key point: Why SC in MOS: accuracy) 2. In one clock period, how much charge does the switched capacitor move from node 1 to node 2? A. CR(V1 + V2) B. CR·V1 only C. CR(V1 - V2) D. CR(V1 - V2)/2 Answer: C. CR charges to V1 on φ1 and to V2 on φ2, so the transferred charge is Δq = CR(V1 - V2). (Key point: Charge transfer) 3. Which expression gives the equivalent resistance of the parallel switched capacitor? A. Req = fc·CR B. Req = 1/(fc·CR) C. Req = CR/fc D. Req = 1/(4·fc·CR) Answer: B. I = Δq/Tc = fc·CR(V1 - V2), so Req = (V1 - V2)/I = 1/(fc·CR). For CR = 1 pF and fc = 100 kHz, Req = 10 MΩ. (Key point: Equivalent resistance) 4. Which condition is needed for the SC resistor model to hold? A. fc much higher than the signal frequency and non-overlapping clocks B. fc equal to the signal frequency C. Overlapping clocks so both switches close together D. fc much lower than the signal frequency Answer: A. V1 and V2 must be nearly constant over a period, so fc must be much higher (50 to 100 times). Non-overlapping clocks stop the nodes being shorted together. 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