--- title: "Interfacing 8-bit ADC using interrupt" subject: "Instrumentation II" chapter: 4 key: "semester_5/instrumentation_ii:adc-interrupt-interface" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/adc-interrupt-interface site: BCT Engineering --- # Interfacing 8-bit ADC using interrupt Instrumentation II · Chapter 4: Interfacing A/D And D/A Converters - Asked in: 2078 Bhadra, 8 marks; 2069 Chaitra, 5 marks (asked 2 times) - Video: [ADC interfacing | introduction | ADC 0808/0809 | MPMC | Lec-45 | Bhanu Priya](https://www.youtube.com/watch?v=Ys_FMNcTzt4) — Education 4u - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/adc-interrupt-interface - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-4 ## Question Explain the principle involved while interfacing an 8-bit ADC using interrupt; including suitable block diagram, process flow diagram and necessary ALP subroutine. ## Short answer Start conversion via OUT 80H, then use RST7.5 interrupt driven by ADC’s EOC. The ISR reads the ADC with IN 80H, stores data, sets a flag, and returns, avoiding polling delays (e.g., 100 µs for ADC0809). ## Answer In interrupt-driven ADC interfacing, the CPU starts the conversion and continues other work. When the ADC finishes it raises its **EOC (end of conversion)** output, which interrupts the 8085, and the interrupt service routine reads the result. This avoids waiting or polling during the conversion time (100 us for ADC0809). #### Block diagram (ADC0809, I/O mapped at 80H) ```text Analog inputs IN0-IN7 | +--------------+ OUT 80H pulse (IOW' + decode) -> START and ALE | ADC 0809 | channel number on D0-D2 -> ADD A, B, C | | IN 80H (IOR' + decode) -> OE | D0-D7 out |--------------------> AD0-AD7 (data bus of 8085) | EOC -------|-------------------> RST 7.5 (8085 interrupt input) | CLK <- 640 kHz (from CLK OUT divided) +--------------+ Vref+ = 5 V, Vref- = 0 ``` RST 7.5 is edge triggered (rising edge) and has the vector 003CH. EOC goes high at the end of conversion and stays high until a new conversion starts. If it were connected to the level-sensitive RST 5.5, it would interrupt again and again after every EI. The rising edge on RST 7.5 is latched, so the CPU is interrupted only once per conversion. #### Process flow ```text MAIN ISR (vector 003CH) Set stack, enable RST 7.5 Save registers EI IN 80H (OE = 1, read data) Clear flag Store data in memory Select channel, OUT 80H Set flag (start conversion) Restore registers Do other work / wait flag EI, RET Use stored data ``` #### ALP ```text ORG 003CH JMP ADCISR ; RST 7.5 vector ORG 2000H START: LXI SP,27FFH MVI A,1BH ; SIM: reset 7.5 latch, MSE=1, mask 6.5 and 5.5, enable 7.5 SIM EI XRA A STA 2051H ; clear flag MVI A,00H ; channel 0 OUT 80H ; ALE and START: conversion begins HERE: LDA 2051H ; flag set by ISR ORA A JZ HERE ; main program can do other work here LDA 2050H ; converted data available HLT ADCISR: PUSH PSW IN 80H ; read ADC output (OE active) STA 2050H ; store result MVI A,01H STA 2051H ; set flag POP PSW EI RET ``` Reading the converted value takes only a few microseconds, and the CPU is free during the whole conversion. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In interrupt-driven ADC interfacing, what is the job of the EOC output? A. It starts the conversion B. It interrupts the 8085 when conversion finishes so the ISR can read the result C. It selects the analog channel D. It enables the ADC output buffer Answer: B. EOC goes high at the end of conversion and drives the interrupt input (RST 5.5), so the CPU need not wait or poll. (Key point: Role of EOC) 2. To which address does RST 5.5 transfer control in the answer's program, and what is placed there? A. 0024H, a JMP to the ISR B. 0034H, the ISR itself C. 002CH, a JMP ADCISR D. 003CH, a HLT Answer: C. RST 5.5 vectors to 002CH, where a JMP ADCISR sends control to the service routine. (Key point: RST 5.5 vector) 3. Why does the ISR execute IN 80H? A. It activates OE through IOR' and decode, so the ADC data is read onto the bus B. It starts a new conversion C. It latches the channel address D. It clears the interrupt mask Answer: A. IN 80H generates IOR' plus decode which drives OE, placing the converted byte on the data bus for the CPU. (Key point: Reading in ISR) 4. After OUT 80H starts the conversion, what does the CPU do in the interrupt method? A. Halts until the ADC finishes B. Repeatedly reads EOC in a tight loop C. Resets the ADC every microsecond D. Continues other work until EOC interrupts it Answer: D. The CPU is free during the whole conversion (about 100 us) and is interrupted only when data is ready. (Key point: Advantage over polling) ## Related in Instrumentation II - [Interfacing 8-channel 8-bit ADC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc0808-8channel) — Instrumentation II, chapter 4 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [Interfacing 10-bit DAC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac10-8085) — Instrumentation II, chapter 4, asked 2× - [ADC at 80H with 8255A: display on port B LEDs](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-8255-80h-leds) — Instrumentation II, chapter 2 - [10-bit DAC triangular wave at 500 Hz](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac10-triangular-500hz) — Instrumentation II, chapter 4 - [Data logger block diagram and operation](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adl-block) — Instrumentation II, chapter 5, asked 6× ## Related in other subjects - [Dual slope ADC block diagram; integral linearity](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adual-slope-integral-linearity) — Advanced Electronics, chapter 3 - [n-bit full adder block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3An-bit-full-adder) — Digital Logic, chapter 5 - [Signal flow graph of G1–G3, H1–H3 block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fcontrol_systems%3Asfg-g1g2g3-h1h2h3) — Control Systems, chapter 3 - [Interrupt and fixed ISR flow of actions](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-fixed-isr-flow) — Embedded System, chapter 5