--- title: "Interfacing 8-channel 8-bit ADC with 8085" subject: "Instrumentation II" chapter: 4 key: "semester_5/instrumentation_ii:adc0808-8channel" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/adc0808-8channel site: BCT Engineering --- # Interfacing 8-channel 8-bit ADC with 8085 Instrumentation II · Chapter 4: Interfacing A/D And D/A Converters - Asked in: 2076 Asoj, 5 marks - Video: [EE309 | Module III | Class 5 | Interfacing ADC to 8085 Microprocessor | KTU | EEE | S5](https://www.youtube.com/watch?v=7OKYp70BjC4) — arun xavier - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/adc0808-8channel - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-4 ## Question With necessary diagram, Explain interfacing of 8 channel 8 bit ADC with 8085 microprocessor along with timing diagram. ## Short answer ADC0808 is interfaced to 8085 via I/O port 80H: OUT 80H pulses ALE and START together with channel number on D0–D2; after EOC rises (~100 µs), IN 80H enables OE and reads the 8-bit data. Clock is 640 kHz, resolution 19.5 mV per count. ## Answer The ADC0808/0809 is an 8-bit successive approximation ADC with an 8-channel analog multiplexer. It needs a clock (10-1280 kHz, typically 640 kHz), and has control pins ADD A, B, C (channel select), ALE (address latch enable), START, EOC (end of conversion) and OE (output enable). #### Interfacing (I/O mapped, port 80H) ```text Analog IN0-IN7 ->+-------------+ | ADC 0808 |-- D0-D7 --> AD0-AD7 (via IN) 8085 D0-D2 ----->| ADD A,B,C | IOW' + A7..A0 | ALE & START |<-- from decoder (OUT 80H) decoder (80H) -->| | IOR' + decoder ->| OE | RST 5.5 / polled<-| EOC | CLK OUT / 4 ---->| CLK 640 kHz | | Vref+=5V, Vref-=0 +-------------+ ``` `OUT 80H` puts the channel number on D0-D2 and gives a pulse on ALE and START together; `IN 80H` makes OE high and reads the data. EOC can be read through an input buffer (polling) or connected to an interrupt input. #### Timing diagram ```text ADD A,B,C ---< channel valid >----------------------- ALE ______/------\______________________________ START ______/------\______________________________ EOC -------------\_____________________/-------- |<-- conversion ~100us -->| OE _________________________________/-----\____ D0-D7 -------------------------------< valid >---- ``` 1. Address is valid; ALE goes high and latches it. 2. START: the rising edge resets the ADC, the falling edge begins conversion; EOC falls (within 8 clock periods). 3. After about 100 us, EOC rises. 4. OE goes high; data appears on D0-D7 (output delay about 250 ns); the CPU reads it. #### Program ```text MVI A,03H ; channel 3 OUT 80H ; address, ALE, START MVI C,FFH DELAY: DCR C JNZ DELAY ; wait more than 100 us (or poll EOC) IN 80H ; read data (OE active) STA 2050H HLT ``` Resolution: 5 V / 256 = 19.5 mV per count. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does OUT 80H do in this interfacing? A. Reads the ADC data B. Puts the channel number on D0-D2 and pulses ALE and START together C. Enables OE D. Resets the 8085 Answer: B. IOW' with the decoded address gives ALE and START, latching the channel and beginning conversion. (Key point: OUT instruction) 2. What do the START edges do? A. Falling edge resets, rising edge begins conversion B. Both edges read data C. Neither affects the ADC D. Rising edge resets the ADC and falling edge begins conversion Answer: D. The rising edge resets internal registers and the falling edge starts conversion; EOC then falls. (Key point: START edges) 3. When is the data valid on D0-D7? A. After EOC rises and OE goes high (IN 80H) B. While EOC is low C. Before START D. Only during ALE Answer: A. Output buffers are tri-state; data appears after conversion completes and OE is high. (Key point: Reading data) 4. With a 640 kHz clock, about how long does conversion take? A. 1 us B. 10 ms C. 100 us D. 1 s Answer: C. The ADC0808 takes about 100 us at 640 kHz, so the program waits longer than that or polls EOC. (Key point: Conversion time) ## Related in Instrumentation II - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [Interfacing 8-bit ADC using interrupt](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-interrupt-interface) — Instrumentation II, chapter 4, asked 2× - [Interfacing 10-bit DAC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac10-8085) — Instrumentation II, chapter 4, asked 2× - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 - [Interfacing: 512-byte RAM with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arag-ram-512-interface) — Instrumentation II, chapter 2 - [ADC with 8085 using 8255: fan and heater control](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-8255-fan-heater) — Instrumentation II, chapter 4 ## Related in other subjects - [Timing diagram of STA 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-sta-8050h) — Microprocessor, chapter 2 - [8085 ALP: odd parity transfer with bit change](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-odd-parity-transfer) — Microprocessor, chapter 2 - [8085 ALP: transfer with bit set/reset](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-set-reset-bit-80h) — Microprocessor, chapter 2 - [Dual slope ADC block diagram; integral linearity](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adual-slope-integral-linearity) — Advanced Electronics, chapter 3