--- title: "8-channel ADC interface with 8255 and 8085" subject: "Instrumentation II" chapter: 4 key: "semester_5/instrumentation_ii:adc8-8255-problem" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/adc8-8255-problem site: BCT Engineering --- # 8-channel ADC interface with 8255 and 8085 Instrumentation II · Chapter 4: Interfacing A/D And D/A Converters - Asked in: 2072 Kartik, 8 marks - Video: [ADC interfacing | with 8086 and 8255 | | MPMC | Lec-46 | Bhanu Priya](https://www.youtube.com/watch?v=TtAsMwhVcAs) — Education 4u - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/adc8-8255-problem - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-4 ## Question To convert an analog signal into digital form, 8-bit ADC is used. The ADC has eight input channels, and channel four is used to capture the incoming analog signal. The address of the desired channel is sent through pins PB0, PB1 and PB2. After at least 50-nanoseconds, this address must be latched. The latching signal is sent using PB4. After another 2.5-microseconds, PB3 is used to initiate the conversion process. The completion of the process is signaled via PC5. The output latch of the ADC can be enabled through PB6, and digital data can be read through port A of 8255-PPI. (i) Draw a circuit showing the interfacing of the ADC module, 8255-PPI and 8085 microprocessor on the basis of the connections described above. (ii) Draw the timing waveforms of all the control and data signals involved in the process. (iii) Provide a flowchart that depicts the ADC process. (iv) Derive port addresses from your circuit diagram and provide the control word. ## Short answer Port A=80H, Port B=81H, Port C=82H, Control register=83H. The control word is 98H (mode 0, port A input, port B output, PC5 input). Channel 4 address 04H is sent on PB0-2, ALE on PB4, START on PB3, OE on PB6, EOC read from PC5. ## Answer #### Assumptions The 8085 is I/O mapped. The 8255 is selected by A7-A2 = 100000, so **Port A = 80H, Port B = 81H, Port C = 82H, Control = 83H**. Channel 4 = address 100 on PB2 PB1 PB0. #### (i) Interfacing circuit ```text 8085 8255A ADC (8-ch, 8-bit) AD0-AD7 (data) -------> D0-D7 IOR' -> RD' IOW' -> WR' RESET OUT -> RESET A0,A1 (latched) -> A0,A1 A7..A2 decoder -> CS' PB0 ------------------> ADD A PB1 ------------------> ADD B PB2 ------------------> ADD C PB3 ------------------> START PB4 ------------------> ALE PB6 ------------------> OE PC5 <------------------ EOC PA0-PA7 <-------------- D0-D7 (output latch) Clock: CLK OUT of 8085 divided to 640 kHz ``` #### Sequence of operation 1. Send channel address 100 (04H) on PB0-PB2. 2. After at least 50 ns, raise ALE (PB4) to latch the address. 3. After 2.5 us, raise START (PB3). The conversion begins on its falling edge. 4. Wait for EOC (PC5) to go high. 5. Raise OE (PB6) and read port A. Then clear OE. #### (ii) Timing waveforms ```text ADD (PB0-2) ---< 100 (channel 4) >---------------------- ALE (PB4) ___________/----\______________________________ START (PB3) ______________________/----\____________________ EOC (PC5) ____________________________\_____________/----- >=50ns >=2.5us conversion (~100us) OE (PB6) ______________________________________/---\____ Data (PA) ---------------------------------------< valid >- ``` #### (iii) Flowchart ```text START -> Initialise 8255 (control word) -> Output channel address 04H to PB0-PB2 -> Set ALE = 1 (PB4), then 0 (latch address) -> Delay >= 2.5 us -> Set START = 1 (PB3), then 0 (start conversion) -> Is EOC (PC5) = 1 ? -- no --> wait -> yes: Set OE = 1 (PB6) -> Read port A (digital data) -> OE = 0 -> END ``` #### (iv) Control word and program Port A input (D4 = 1), port B output (D1 = 0), PC5 is in upper port C and is an input (D3 = 1), lower C unused (D0 = 0), mode 0 for both groups: 1001 1000 = **98H**. ```text MVI A,98H OUT 83H MVI A,04H ; channel 4 address OUT 81H MVI A,14H ; ALE = 1 (PB4) with address OUT 81H MVI A,04H ; ALE = 0 OUT 81H NOP NOP ; > 2.5 us delay (at 3 MHz, 3 x 1.33 us = 4 us) NOP MVI A,0CH ; START = 1 (PB3) with address OUT 81H MVI A,04H ; START = 0 OUT 81H WAIT: IN 82H ANI 20H ; EOC (PC5) JZ WAIT MVI A,44H ; OE = 1 (PB6) OUT 81H IN 80H ; read data MVI A,04H OUT 81H ; OE = 0 HLT ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Port A input, port B output, PC5 (upper C) input, lower C unused as output, mode 0: what control word results? A. 90H B. 88H C. 9BH D. 98H Answer: D. D7=1, D4=1 (A in), D3=1 (C upper in), D1=0 (B out), D0=0 gives 1001 1000 = 98H. (Key point: Control word) 2. What is the correct order of ADC control signals for this design? A. Address on PB0-2, ALE pulse after at least 50 ns, START after about 2.5 us, wait for EOC B. START first, then address, then ALE C. OE first, then address, then START D. ALE, then OE, then address Answer: A. The address must be stable before ALE latches it, then START begins conversion, then EOC is awaited. (Key point: Control sequence) 3. With the 8255 selected by A7-A2 = 100000, what is the address of port B and the data for channel 4 on PB2 PB1 PB0? A. 80H and 03H B. 83H and 100H C. 81H and 04H D. 82H and 08H Answer: C. A1A0 = 01 gives 81H for port B; channel 4 is binary 100 = 04H. (Key point: Port addresses) 4. When is the output latch enabled (PB6) and the data read? A. Before ALE B. After EOC goes high; then port A is read and OE cleared C. During the START pulse D. Only after a reset Answer: B. Data is valid only after conversion is complete, so OE is raised after EOC, port A read, then OE cleared. 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