---
title: "Clock jitter on a motherboard"
subject: "Instrumentation II"
chapter: 6
key: "semester_5/instrumentation_ii:clock-jitter-motherboard"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/clock-jitter-motherboard
site: BCT Engineering
---

# Clock jitter on a motherboard

Instrumentation II · Chapter 6: Grounding And Shielding

- Asked in: 2074 Asoj, 4 marks
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/clock-jitter-motherboard
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-6

## Question

A faulty computer motherboard has severe clock jitter. The crystal producing the clock pulses is functioning properly, but clock signals arriving at various motherboard chips suffer from jitter. Discuss the source of the problem and provide some remedies.

## Short answer

Jitter arises from crosstalk, ground bounce, reflections from unterminated traces, and poor decoupling on the clock distribution net. Remedies include routing clocks over a solid ground plane, keeping traces short and guarded, adding series termination, and using adequate decoupling capacitors and matched‑length clock buffers.

## Answer

Since the crystal is good, the jitter appears **after** the clock leaves the source, so it is caused by the distribution of the clock on the board. **Jitter** is the variation of the clock edge from its ideal time, caused by noise adding to the signal near the switching threshold.

#### Likely sources
1. **Crosstalk:** clock traces running parallel to other fast signals pick up noise by capacitive and inductive coupling.
2. **Power supply/ground noise:** simultaneous switching causes ground bounce and supply ripple, shifting the threshold crossing time. Poor decoupling worsens this.
3. **Impedance mismatch and reflections:** unterminated or long clock traces reflect the wave, and the reflections add to the edge.
4. **Poor ground return / split planes:** the clock return current detours, increasing loop area and noise.
5. **EMI** from nearby switching regulators or other devices.
6. Different trace lengths to different chips (skew) and excessive loading.

#### Remedies
- Route clocks short, direct, and on a layer next to a solid ground plane.
- Keep them away from noisy/parallel signals (3W rule) or surround with ground guard traces.
- Terminate the line (series resistor near the source, or parallel/Thevenin at the end) to match impedance.
- Add decoupling capacitors (0.1 uF) at each chip and bulk capacitors; use separate analog/digital supplies.
- Use a clock buffer/PLL with equal-length traces to each chip.
- Use a ferrite bead/LC filter on the clock supply, and shield if needed.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why does the problem arise after the crystal?
   A. The crystal ages
   B. The clock is corrupted in distribution on the board
   C. The CPU is too fast
   D. The battery fails
   Answer: B. The crystal is good. (Key point: Location)

2. Which is a likely cause?
   A. Low humidity
   B. Weak crystal
   C. Crosstalk and ground bounce shifting the threshold crossing
   D. Too many decoupling caps
   Answer: C. Noise near threshold shifts edge timing. (Key point: Cause)

3. Why terminate the clock line?
   A. To raise frequency
   B. To slow the crystal
   C. To add skew
   D. To stop reflections by matching impedance
   Answer: D. Unterminated traces reflect. (Key point: Termination)

4. Which is a remedy?
   A. Short traces over a ground plane with 0.1 uF decoupling at each chip
   B. Long parallel routing
   C. Remove ground plane
   D. Remove decoupling
   Answer: A. Clean routing and decoupling reduce jitter. (Key point: Remedy)

## Related in Instrumentation II

- [ISA bus signals; replacement by PCI bus](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aisa-pci-bus) — Instrumentation II, chapter 2
- [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4
- [USB to RS-232 adapter design](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-rs232-adapter) — Instrumentation II, chapter 3
- [Case study: feasibility, drawbacks, convincing](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Acs-2072kartik-feasibility) — Instrumentation II, chapter 10

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